Lines Matching +full:gic +full:- +full:v3
1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
3 * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
14 soc_refclk50mhz: clock-50000000 {
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-frequency = <50000000>;
18 clock-output-names = "apb_pclk";
21 soc_refclk85mhz: clock-85000000 {
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <85000000>;
25 clock-output-names = "iofpga:aclk";
29 #address-cells = <2>;
30 #size-cells = <0>;
36 enable-method = "psci";
38 i-cache-size = <0x10000>;
39 i-cache-line-size = <64>;
40 i-cache-sets = <512>;
41 d-cache-size = <0x10000>;
42 d-cache-line-size = <64>;
43 d-cache-sets = <512>;
44 next-level-cache = <&l2_0>;
47 l2_0: l2-cache {
49 cache-level = <2>;
51 cache-size = <0x100000>;
52 cache-line-size = <64>;
53 cache-sets = <2048>;
54 cache-unified;
55 next-level-cache = <&l3_0>;
63 enable-method = "psci";
65 i-cache-size = <0x10000>;
66 i-cache-line-size = <64>;
67 i-cache-sets = <512>;
68 d-cache-size = <0x10000>;
69 d-cache-line-size = <64>;
70 d-cache-sets = <512>;
71 next-level-cache = <&l2_1>;
74 l2_1: l2-cache {
76 cache-level = <2>;
78 cache-size = <0x100000>;
79 cache-line-size = <64>;
80 cache-sets = <2048>;
81 cache-unified;
82 next-level-cache = <&l3_0>;
90 enable-method = "psci";
92 i-cache-size = <0x10000>;
93 i-cache-line-size = <64>;
94 i-cache-sets = <512>;
95 d-cache-size = <0x10000>;
96 d-cache-line-size = <64>;
97 d-cache-sets = <512>;
98 next-level-cache = <&l2_2>;
101 l2_2: l2-cache {
103 cache-level = <2>;
105 cache-size = <0x100000>;
106 cache-line-size = <64>;
107 cache-sets = <2048>;
108 cache-unified;
109 next-level-cache = <&l3_0>;
117 enable-method = "psci";
119 i-cache-size = <0x10000>;
120 i-cache-line-size = <64>;
121 i-cache-sets = <512>;
122 d-cache-size = <0x10000>;
123 d-cache-line-size = <64>;
124 d-cache-sets = <512>;
125 next-level-cache = <&l2_3>;
128 l2_3: l2-cache {
130 cache-level = <2>;
132 cache-size = <0x100000>;
133 cache-line-size = <64>;
134 cache-sets = <2048>;
135 cache-unified;
136 next-level-cache = <&l3_0>;
140 l3_0: l3-cache {
142 cache-level = <3>;
143 cache-size = <0x100000>;
144 cache-unified;
149 interrupt-parent = <&gic>;
153 mbox-names = "tx", "rx";
156 #address-cells = <1>;
157 #size-cells = <0>;
161 #clock-cells = <1>;
166 #clock-cells = <1>;
174 /* [0x80000000-0xffffffff] */
180 /* [0x8080000000-0x83f7ffffff] */
185 compatible = "arm,rainier-pmu";
190 compatible = "arm,psci-0.2";
194 reserved-memory {
195 #address-cells = <2>;
196 #size-cells = <2>;
199 secure-firmware@ff000000 {
201 no-map;
205 spe-pmu {
206 compatible = "arm,statistical-profiling-extension-v1";
211 compatible = "simple-bus";
212 #address-cells = <2>;
213 #size-cells = <2>;
214 interrupt-parent = <&gic>;
222 clock-names = "uartclk", "apb_pclk";
227 gic: interrupt-controller@30000000 { label
228 compatible = "arm,gic-v3";
234 #interrupt-cells = <3>;
235 interrupt-controller;
237 #address-cells = <2>;
238 #size-cells = <2>;
241 its1: msi-controller@30040000 {
242 compatible = "arm,gic-v3-its";
245 msi-controller;
246 #msi-cells = <1>;
249 its2: msi-controller@30060000 {
250 compatible = "arm,gic-v3-its";
253 msi-controller;
254 #msi-cells = <1>;
257 its_ccix: msi-controller@30080000 {
258 compatible = "arm,gic-v3-its";
261 msi-controller;
262 #msi-cells = <1>;
265 its_pcie: msi-controller@300a0000 {
266 compatible = "arm,gic-v3-its";
269 msi-controller;
270 #msi-cells = <1>;
275 compatible = "arm,smmu-v3";
281 interrupt-names = "eventq", "gerror", "cmdq-sync";
282 #iommu-cells = <1>;
286 compatible = "arm,mhu-doorbell", "arm,primecell";
291 #mbox-cells = <2>;
293 clock-names = "apb_pclk";
297 compatible = "mmio-sram";
301 #address-cells = <1>;
302 #size-cells = <1>;
304 cpu_scp_hpri0: scp-sram@0 {
305 compatible = "arm,scmi-shmem";
309 cpu_scp_hpri1: scp-sram@80 {
310 compatible = "arm,scmi-shmem";
317 compatible = "arm,armv8-timer";