Lines Matching +full:entry +full:- +full:latency +full:- +full:us
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/arm/coresight-cti-dt.h>
13 #include "juno-base.dtsi"
14 #include "juno-cs-r1r2.dtsi"
18 compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
28 stdout-path = "serial0:115200n8";
32 compatible = "arm,psci-0.2";
37 #address-cells = <2>;
38 #size-cells = <0>;
40 cpu-map {
66 idle-states {
67 entry-method = "psci";
69 CPU_SLEEP_0: cpu-sleep-0 {
70 compatible = "arm,idle-state";
71 arm,psci-suspend-param = <0x0010000>;
72 local-timer-stop;
73 entry-latency-us = <300>;
74 exit-latency-us = <1200>;
75 min-residency-us = <2000>;
78 CLUSTER_SLEEP_0: cluster-sleep-0 {
79 compatible = "arm,idle-state";
80 arm,psci-suspend-param = <0x1010000>;
81 local-timer-stop;
82 entry-latency-us = <400>;
83 exit-latency-us = <1200>;
84 min-residency-us = <2500>;
89 compatible = "arm,cortex-a72";
92 enable-method = "psci";
93 i-cache-size = <0xc000>;
94 i-cache-line-size = <64>;
95 i-cache-sets = <256>;
96 d-cache-size = <0x8000>;
97 d-cache-line-size = <64>;
98 d-cache-sets = <256>;
99 next-level-cache = <&A72_L2>;
101 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
102 capacity-dmips-mhz = <1024>;
103 dynamic-power-coefficient = <450>;
107 compatible = "arm,cortex-a72";
110 enable-method = "psci";
111 i-cache-size = <0xc000>;
112 i-cache-line-size = <64>;
113 i-cache-sets = <256>;
114 d-cache-size = <0x8000>;
115 d-cache-line-size = <64>;
116 d-cache-sets = <256>;
117 next-level-cache = <&A72_L2>;
119 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
120 capacity-dmips-mhz = <1024>;
121 dynamic-power-coefficient = <450>;
125 compatible = "arm,cortex-a53";
128 enable-method = "psci";
129 i-cache-size = <0x8000>;
130 i-cache-line-size = <64>;
131 i-cache-sets = <256>;
132 d-cache-size = <0x8000>;
133 d-cache-line-size = <64>;
134 d-cache-sets = <128>;
135 next-level-cache = <&A53_L2>;
137 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
138 capacity-dmips-mhz = <485>;
139 dynamic-power-coefficient = <140>;
143 compatible = "arm,cortex-a53";
146 enable-method = "psci";
147 i-cache-size = <0x8000>;
148 i-cache-line-size = <64>;
149 i-cache-sets = <256>;
150 d-cache-size = <0x8000>;
151 d-cache-line-size = <64>;
152 d-cache-sets = <128>;
153 next-level-cache = <&A53_L2>;
155 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
156 capacity-dmips-mhz = <485>;
157 dynamic-power-coefficient = <140>;
161 compatible = "arm,cortex-a53";
164 enable-method = "psci";
165 i-cache-size = <0x8000>;
166 i-cache-line-size = <64>;
167 i-cache-sets = <256>;
168 d-cache-size = <0x8000>;
169 d-cache-line-size = <64>;
170 d-cache-sets = <128>;
171 next-level-cache = <&A53_L2>;
173 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
174 capacity-dmips-mhz = <485>;
175 dynamic-power-coefficient = <140>;
179 compatible = "arm,cortex-a53";
182 enable-method = "psci";
183 i-cache-size = <0x8000>;
184 i-cache-line-size = <64>;
185 i-cache-sets = <256>;
186 d-cache-size = <0x8000>;
187 d-cache-line-size = <64>;
188 d-cache-sets = <128>;
189 next-level-cache = <&A53_L2>;
191 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
192 capacity-dmips-mhz = <485>;
193 dynamic-power-coefficient = <140>;
196 A72_L2: l2-cache0 {
198 cache-unified;
199 cache-size = <0x200000>;
200 cache-line-size = <64>;
201 cache-sets = <2048>;
202 cache-level = <2>;
205 A53_L2: l2-cache1 {
207 cache-unified;
208 cache-size = <0x100000>;
209 cache-line-size = <64>;
210 cache-sets = <1024>;
211 cache-level = <2>;
215 pmu-a72 {
216 compatible = "arm,cortex-a72-pmu";
219 interrupt-affinity = <&A72_0>,
223 pmu-a53 {
224 compatible = "arm,cortex-a53-pmu";
229 interrupt-affinity = <&A53_0>,
289 remote-endpoint = <&csys2_funnel_in_port0>;
293 remote-endpoint = <&csys2_funnel_out_port>;
297 remote-endpoint = <&stm_out_port>;
301 remote-endpoint = <&csys1_funnel_in_port0>;