Lines Matching +full:entry +full:- +full:latency +full:- +full:us
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/arm/coresight-cti-dt.h>
13 #include "juno-base.dtsi"
14 #include "juno-cs-r1r2.dtsi"
18 compatible = "arm,juno-r1", "arm,juno", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
28 stdout-path = "serial0:115200n8";
32 compatible = "arm,psci-0.2";
37 #address-cells = <2>;
38 #size-cells = <0>;
40 cpu-map {
66 idle-states {
67 entry-method = "psci";
69 CPU_SLEEP_0: cpu-sleep-0 {
70 compatible = "arm,idle-state";
71 arm,psci-suspend-param = <0x0010000>;
72 local-timer-stop;
73 entry-latency-us = <300>;
74 exit-latency-us = <1200>;
75 min-residency-us = <2000>;
78 CLUSTER_SLEEP_0: cluster-sleep-0 {
79 compatible = "arm,idle-state";
80 arm,psci-suspend-param = <0x1010000>;
81 local-timer-stop;
82 entry-latency-us = <400>;
83 exit-latency-us = <1200>;
84 min-residency-us = <2500>;
89 compatible = "arm,cortex-a57";
92 enable-method = "psci";
93 i-cache-size = <0xc000>;
94 i-cache-line-size = <64>;
95 i-cache-sets = <256>;
96 d-cache-size = <0x8000>;
97 d-cache-line-size = <64>;
98 d-cache-sets = <256>;
99 next-level-cache = <&A57_L2>;
101 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
102 capacity-dmips-mhz = <1024>;
106 compatible = "arm,cortex-a57";
109 enable-method = "psci";
110 i-cache-size = <0xc000>;
111 i-cache-line-size = <64>;
112 i-cache-sets = <256>;
113 d-cache-size = <0x8000>;
114 d-cache-line-size = <64>;
115 d-cache-sets = <256>;
116 next-level-cache = <&A57_L2>;
118 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
119 capacity-dmips-mhz = <1024>;
123 compatible = "arm,cortex-a53";
126 enable-method = "psci";
127 i-cache-size = <0x8000>;
128 i-cache-line-size = <64>;
129 i-cache-sets = <256>;
130 d-cache-size = <0x8000>;
131 d-cache-line-size = <64>;
132 d-cache-sets = <128>;
133 next-level-cache = <&A53_L2>;
135 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
136 capacity-dmips-mhz = <578>;
140 compatible = "arm,cortex-a53";
143 enable-method = "psci";
144 i-cache-size = <0x8000>;
145 i-cache-line-size = <64>;
146 i-cache-sets = <256>;
147 d-cache-size = <0x8000>;
148 d-cache-line-size = <64>;
149 d-cache-sets = <128>;
150 next-level-cache = <&A53_L2>;
152 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
153 capacity-dmips-mhz = <578>;
157 compatible = "arm,cortex-a53";
160 enable-method = "psci";
161 i-cache-size = <0x8000>;
162 i-cache-line-size = <64>;
163 i-cache-sets = <256>;
164 d-cache-size = <0x8000>;
165 d-cache-line-size = <64>;
166 d-cache-sets = <128>;
167 next-level-cache = <&A53_L2>;
169 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
170 capacity-dmips-mhz = <578>;
174 compatible = "arm,cortex-a53";
177 enable-method = "psci";
178 i-cache-size = <0x8000>;
179 i-cache-line-size = <64>;
180 i-cache-sets = <256>;
181 d-cache-size = <0x8000>;
182 d-cache-line-size = <64>;
183 d-cache-sets = <128>;
184 next-level-cache = <&A53_L2>;
186 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
187 capacity-dmips-mhz = <578>;
190 A57_L2: l2-cache0 {
192 cache-unified;
193 cache-size = <0x200000>;
194 cache-line-size = <64>;
195 cache-sets = <2048>;
196 cache-level = <2>;
199 A53_L2: l2-cache1 {
201 cache-unified;
202 cache-size = <0x100000>;
203 cache-line-size = <64>;
204 cache-sets = <1024>;
205 cache-level = <2>;
209 pmu-a57 {
210 compatible = "arm,cortex-a57-pmu";
213 interrupt-affinity = <&A57_0>,
217 pmu-a53 {
218 compatible = "arm,cortex-a53-pmu";
223 interrupt-affinity = <&A53_0>,
283 remote-endpoint = <&csys2_funnel_in_port0>;
287 remote-endpoint = <&csys2_funnel_out_port>;
291 remote-endpoint = <&stm_out_port>;
295 remote-endpoint = <&csys1_funnel_in_port0>;