Lines Matching +full:0 +full:x1d0000
13 #clock-cells = <0>;
20 #clock-cells = <0>;
27 #clock-cells = <0>;
34 #clock-cells = <0>;
55 gpios = <&iofpga_gpio0 0 0x4>;
62 gpios = <&iofpga_gpio0 1 0x4>;
69 gpios = <&iofpga_gpio0 2 0x4>;
76 gpios = <&iofpga_gpio0 3 0x4>;
83 gpios = <&iofpga_gpio0 4 0x4>;
90 gpios = <&iofpga_gpio0 5 0x4>;
98 ranges = <0 0x8000000 0 0x8000000 0x18000000>;
104 ranges = <0 0 0 0x08000000 0x04000000>,
105 <1 0 0 0x14000000 0x04000000>,
106 <2 0 0 0x18000000 0x04000000>,
107 <3 0 0 0x1c000000 0x04000000>,
108 <4 0 0 0x0c000000 0x04000000>,
109 <5 0 0 0x10000000 0x04000000>;
110 arm,hbi = <0x252>;
111 arm,vexpress,site = <0>;
113 flash@0 {
116 reg = <0 0x00000000 0x04000000>;
132 reg = <2 0x00000000 0x10000>;
147 ranges = <0 3 0 0x200000>;
151 reg = <0x020000 0x1000>;
156 assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
163 reg = <0x010000 0x1000>;
164 ranges = <0x0 0x10000 0x1000>;
168 led@8,0 {
170 reg = <0x08 0x04>;
171 offset = <0x08>;
172 mask = <0x01>;
173 label = "vexpress:0";
179 reg = <0x08 0x04>;
180 offset = <0x08>;
181 mask = <0x02>;
188 reg = <0x08 0x04>;
189 offset = <0x08>;
190 mask = <0x04>;
197 reg = <0x08 0x04>;
198 offset = <0x08>;
199 mask = <0x08>;
206 reg = <0x08 0x04>;
207 offset = <0x08>;
208 mask = <0x10>;
215 reg = <0x08 0x04>;
216 offset = <0x08>;
217 mask = <0x20>;
224 reg = <0x08 0x04>;
225 offset = <0x08>;
226 mask = <0x40>;
232 reg = <0x08 0x04>;
233 offset = <0x08>;
234 mask = <0x80>;
242 reg = <0x050000 0x1000>;
244 /* cd-gpios = <&v2m_mmc_gpios 0 0>;
245 wp-gpios = <&v2m_mmc_gpios 1 0>; */
254 reg = <0x060000 0x1000>;
262 reg = <0x070000 0x1000>;
270 reg = <0x0f0000 0x10000>;
278 reg = <0x110000 0x10000>;
280 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&mb_clk24mhz>;
286 reg = <0x120000 0x10000>;
294 reg = <0x170000 0x10000>;
295 interrupts = <0>;
302 reg = <0x1d0000 0x1000>;