Lines Matching +full:rtsm +full:- +full:display
1 // SPDX-License-Identifier: GPL-2.0
5 * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "rtsm_ve-motherboard.dtsi"
18 #include "rtsm_ve-motherboard-rs2.dtsi"
22 compatible = "arm,fvp-base-revc", "arm,vexpress";
23 interrupt-parent = <&gic>;
24 #address-cells = <2>;
25 #size-cells = <2>;
28 stdout-path = "serial0:115200n8";
39 compatible = "arm,psci-0.2";
44 #address-cells = <2>;
45 #size-cells = <0>;
51 enable-method = "psci";
52 i-cache-size = <0x8000>;
53 i-cache-line-size = <64>;
54 i-cache-sets = <256>;
55 d-cache-size = <0x8000>;
56 d-cache-line-size = <64>;
57 d-cache-sets = <256>;
58 next-level-cache = <&C0_L2>;
64 enable-method = "psci";
65 i-cache-size = <0x8000>;
66 i-cache-line-size = <64>;
67 i-cache-sets = <256>;
68 d-cache-size = <0x8000>;
69 d-cache-line-size = <64>;
70 d-cache-sets = <256>;
71 next-level-cache = <&C0_L2>;
77 enable-method = "psci";
78 i-cache-size = <0x8000>;
79 i-cache-line-size = <64>;
80 i-cache-sets = <256>;
81 d-cache-size = <0x8000>;
82 d-cache-line-size = <64>;
83 d-cache-sets = <256>;
84 next-level-cache = <&C0_L2>;
90 enable-method = "psci";
91 i-cache-size = <0x8000>;
92 i-cache-line-size = <64>;
93 i-cache-sets = <256>;
94 d-cache-size = <0x8000>;
95 d-cache-line-size = <64>;
96 d-cache-sets = <256>;
97 next-level-cache = <&C0_L2>;
103 enable-method = "psci";
104 i-cache-size = <0x8000>;
105 i-cache-line-size = <64>;
106 i-cache-sets = <256>;
107 d-cache-size = <0x8000>;
108 d-cache-line-size = <64>;
109 d-cache-sets = <256>;
110 next-level-cache = <&C1_L2>;
116 enable-method = "psci";
117 i-cache-size = <0x8000>;
118 i-cache-line-size = <64>;
119 i-cache-sets = <256>;
120 d-cache-size = <0x8000>;
121 d-cache-line-size = <64>;
122 d-cache-sets = <256>;
123 next-level-cache = <&C1_L2>;
129 enable-method = "psci";
130 i-cache-size = <0x8000>;
131 i-cache-line-size = <64>;
132 i-cache-sets = <256>;
133 d-cache-size = <0x8000>;
134 d-cache-line-size = <64>;
135 d-cache-sets = <256>;
136 next-level-cache = <&C1_L2>;
142 enable-method = "psci";
143 i-cache-size = <0x8000>;
144 i-cache-line-size = <64>;
145 i-cache-sets = <256>;
146 d-cache-size = <0x8000>;
147 d-cache-line-size = <64>;
148 d-cache-sets = <256>;
149 next-level-cache = <&C1_L2>;
151 C0_L2: l2-cache0 {
153 cache-size = <0x80000>;
154 cache-line-size = <64>;
155 cache-sets = <512>;
156 cache-level = <2>;
157 cache-unified;
160 C1_L2: l2-cache1 {
162 cache-size = <0x80000>;
163 cache-line-size = <64>;
164 cache-sets = <512>;
165 cache-level = <2>;
166 cache-unified;
176 reserved-memory {
177 #address-cells = <2>;
178 #size-cells = <2>;
184 compatible = "shared-dma-pool";
186 no-map;
190 gic: interrupt-controller@2f000000 {
191 compatible = "arm,gic-v3";
192 #interrupt-cells = <3>;
193 #address-cells = <2>;
194 #size-cells = <2>;
196 interrupt-controller;
204 its: msi-controller@2f020000 {
205 #msi-cells = <1>;
206 compatible = "arm,gic-v3-its";
208 msi-controller;
213 compatible = "arm,armv8-timer";
221 compatible = "arm,armv8-pmuv3";
225 spe-pmu {
226 compatible = "arm,statistical-profiling-extension-v1";
231 #address-cells = <0x3>;
232 #size-cells = <0x2>;
233 #interrupt-cells = <0x1>;
234 compatible = "pci-host-ecam-generic";
236 bus-range = <0x0 0x1>;
239 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
243 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
244 msi-map = <0x0 &its 0x0 0x10000>;
245 iommu-map = <0x0 &smmu 0x0 0x10000>;
247 dma-coherent;
248 ats-supported;
252 compatible = "arm,smmu-v3";
258 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
259 dma-coherent;
260 #iommu-cells = <1>;
261 msi-parent = <&its 0x10000>;
265 compatible = "arm,rtsm-display";
268 remote-endpoint = <&clcd_pads>;
274 #interrupt-cells = <1>;
275 interrupt-map-mask = <0 0 63>;
276 interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,