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1 // SPDX-License-Identifier: GPL-2.0
5 * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "rtsm_ve-motherboard.dtsi"
18 #include "rtsm_ve-motherboard-rs2.dtsi"
22 compatible = "arm,fvp-base-revc", "arm,vexpress";
23 interrupt-parent = <&gic>;
24 #address-cells = <2>;
25 #size-cells = <2>;
28 stdout-path = "serial0:115200n8";
39 compatible = "arm,psci-0.2";
44 #address-cells = <2>;
45 #size-cells = <0>;
47 idle-states {
48 entry-method = "psci";
50 CPU_SLEEP_0: cpu-sleep-0 {
51 compatible = "arm,idle-state";
52 local-timer-stop;
53 arm,psci-suspend-param = <0x0010000>;
54 entry-latency-us = <40>;
55 exit-latency-us = <100>;
56 min-residency-us = <150>;
60 CLUSTER_SLEEP_0: cluster-sleep-0 {
61 compatible = "arm,idle-state";
62 local-timer-stop;
63 arm,psci-suspend-param = <0x1010000>;
64 entry-latency-us = <500>;
65 exit-latency-us = <1000>;
66 min-residency-us = <2500>;
75 enable-method = "psci";
76 i-cache-size = <0x8000>;
77 i-cache-line-size = <64>;
78 i-cache-sets = <256>;
79 d-cache-size = <0x8000>;
80 d-cache-line-size = <64>;
81 d-cache-sets = <256>;
82 next-level-cache = <&C0_L2>;
83 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
89 enable-method = "psci";
90 i-cache-size = <0x8000>;
91 i-cache-line-size = <64>;
92 i-cache-sets = <256>;
93 d-cache-size = <0x8000>;
94 d-cache-line-size = <64>;
95 d-cache-sets = <256>;
96 next-level-cache = <&C0_L2>;
97 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
103 enable-method = "psci";
104 i-cache-size = <0x8000>;
105 i-cache-line-size = <64>;
106 i-cache-sets = <256>;
107 d-cache-size = <0x8000>;
108 d-cache-line-size = <64>;
109 d-cache-sets = <256>;
110 next-level-cache = <&C0_L2>;
111 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
117 enable-method = "psci";
118 i-cache-size = <0x8000>;
119 i-cache-line-size = <64>;
120 i-cache-sets = <256>;
121 d-cache-size = <0x8000>;
122 d-cache-line-size = <64>;
123 d-cache-sets = <256>;
124 next-level-cache = <&C0_L2>;
125 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
131 enable-method = "psci";
132 i-cache-size = <0x8000>;
133 i-cache-line-size = <64>;
134 i-cache-sets = <256>;
135 d-cache-size = <0x8000>;
136 d-cache-line-size = <64>;
137 d-cache-sets = <256>;
138 next-level-cache = <&C1_L2>;
139 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
145 enable-method = "psci";
146 i-cache-size = <0x8000>;
147 i-cache-line-size = <64>;
148 i-cache-sets = <256>;
149 d-cache-size = <0x8000>;
150 d-cache-line-size = <64>;
151 d-cache-sets = <256>;
152 next-level-cache = <&C1_L2>;
153 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
159 enable-method = "psci";
160 i-cache-size = <0x8000>;
161 i-cache-line-size = <64>;
162 i-cache-sets = <256>;
163 d-cache-size = <0x8000>;
164 d-cache-line-size = <64>;
165 d-cache-sets = <256>;
166 next-level-cache = <&C1_L2>;
167 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
173 enable-method = "psci";
174 i-cache-size = <0x8000>;
175 i-cache-line-size = <64>;
176 i-cache-sets = <256>;
177 d-cache-size = <0x8000>;
178 d-cache-line-size = <64>;
179 d-cache-sets = <256>;
180 next-level-cache = <&C1_L2>;
181 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
183 C0_L2: l2-cache0 {
184 compatible = "cache";
185 cache-size = <0x80000>;
186 cache-line-size = <64>;
187 cache-sets = <512>;
188 cache-level = <2>;
189 cache-unified;
192 C1_L2: l2-cache1 {
193 compatible = "cache";
194 cache-size = <0x80000>;
195 cache-line-size = <64>;
196 cache-sets = <512>;
197 cache-level = <2>;
198 cache-unified;
208 reserved-memory {
209 #address-cells = <2>;
210 #size-cells = <2>;
216 compatible = "shared-dma-pool";
218 no-map;
222 gic: interrupt-controller@2f000000 {
223 compatible = "arm,gic-v3";
224 #interrupt-cells = <3>;
225 #address-cells = <2>;
226 #size-cells = <2>;
228 interrupt-controller;
236 its: msi-controller@2f020000 {
237 #msi-cells = <1>;
238 compatible = "arm,gic-v3-its";
240 msi-controller;
245 compatible = "arm,armv8-timer";
253 compatible = "arm,armv7-timer-mem";
256 #address-cells = <1>;
257 #size-cells = <1>;
259 frame-number = <1>;
266 compatible = "arm,armv8-pmuv3";
270 spe-pmu {
271 compatible = "arm,statistical-profiling-extension-v1";
275 ete-0 {
276 compatible = "arm,embedded-trace-extension";
281 ete-1 {
282 compatible = "arm,embedded-trace-extension";
287 ete-2 {
288 compatible = "arm,embedded-trace-extension";
293 ete-3 {
294 compatible = "arm,embedded-trace-extension";
299 ete-4 {
300 compatible = "arm,embedded-trace-extension";
305 ete-5 {
306 compatible = "arm,embedded-trace-extension";
311 ete-6 {
312 compatible = "arm,embedded-trace-extension";
317 ete-7 {
318 compatible = "arm,embedded-trace-extension";
324 compatible = "arm,trace-buffer-extension";
330 #address-cells = <0x3>;
331 #size-cells = <0x2>;
332 #interrupt-cells = <0x1>;
333 compatible = "pci-host-ecam-generic";
335 bus-range = <0x0 0xff>;
338 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
342 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
343 msi-map = <0x0 &its 0x0 0x10000>;
344 iommu-map = <0x0 &smmu 0x0 0x10000>;
346 dma-coherent;
347 ats-supported;
351 compatible = "arm,smmu-v3";
357 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
358 dma-coherent;
359 #iommu-cells = <1>;
360 msi-parent = <&its 0x10000>;
364 compatible = "arm,rtsm-display";
367 remote-endpoint = <&clcd_pads>;
373 #interrupt-cells = <1>;
374 interrupt-map-mask = <0 0 63>;
375 interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,