Lines Matching +full:0 +full:x8000
15 /memreserve/ 0x80000000 0x00010000;
45 #size-cells = <0>;
50 CPU_SLEEP_0: cpu-sleep-0 {
53 arm,psci-suspend-param = <0x0010000>;
60 CLUSTER_SLEEP_0: cluster-sleep-0 {
63 arm,psci-suspend-param = <0x1010000>;
71 cpu0: cpu@0 {
74 reg = <0x0 0x000>;
76 i-cache-size = <0x8000>;
79 d-cache-size = <0x8000>;
88 reg = <0x0 0x100>;
90 i-cache-size = <0x8000>;
93 d-cache-size = <0x8000>;
102 reg = <0x0 0x200>;
104 i-cache-size = <0x8000>;
107 d-cache-size = <0x8000>;
116 reg = <0x0 0x300>;
118 i-cache-size = <0x8000>;
121 d-cache-size = <0x8000>;
130 reg = <0x0 0x10000>;
132 i-cache-size = <0x8000>;
135 d-cache-size = <0x8000>;
144 reg = <0x0 0x10100>;
146 i-cache-size = <0x8000>;
149 d-cache-size = <0x8000>;
158 reg = <0x0 0x10200>;
160 i-cache-size = <0x8000>;
163 d-cache-size = <0x8000>;
172 reg = <0x0 0x10300>;
174 i-cache-size = <0x8000>;
177 d-cache-size = <0x8000>;
185 cache-size = <0x80000>;
194 cache-size = <0x80000>;
204 reg = <0x00000000 0x80000000 0 0x7c000000>,
205 <0x00000008 0x80000000 0 0x80000000>;
213 /* Chipselect 2,00000000 is physically at 0x18000000 */
217 reg = <0x00000000 0x18000000 0 0x00800000>;
229 reg = <0x0 0x2f000000 0 0x10000>, // GICD
230 <0x0 0x2f100000 0 0x200000>, // GICR
231 <0x0 0x2c000000 0 0x2000>, // GICC
232 <0x0 0x2c010000 0 0x2000>, // GICH
233 <0x0 0x2c02f000 0 0x2000>; // GICV
239 reg = <0x0 0x2f020000 0x0 0x20000>; // GITS
254 reg = <0x0 0x2a810000 0x0 0x10000>;
255 ranges = <0 0x0 0x2a820000 0x20000>;
261 reg = <0x10000 0x10000>;
275 ete-0 {
330 #address-cells = <0x3>;
331 #size-cells = <0x2>;
332 #interrupt-cells = <0x1>;
335 bus-range = <0x0 0xff>;
336 reg = <0x0 0x40000000 0x0 0x10000000>;
337 ranges = <0x2000000 0x0 0x50000000 0x0 0x50000000 0x0 0x10000000>;
338 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
339 <0 0 0 2 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
340 <0 0 0 3 &gic 0 0 GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
341 <0 0 0 4 &gic 0 0 GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
342 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
343 msi-map = <0x0 &its 0x0 0x10000>;
344 iommu-map = <0x0 &smmu 0x0 0x10000>;
352 reg = <0x0 0x2b400000 0x0 0x100000>;
360 msi-parent = <&its 0x10000>;
374 interrupt-map-mask = <0 0 63>;
375 interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
376 <0 0 1 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
377 <0 0 2 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
378 <0 0 3 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
379 <0 0 4 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
380 <0 0 5 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
381 <0 0 6 &gic 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
382 <0 0 7 &gic 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
383 <0 0 8 &gic 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
384 <0 0 9 &gic 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
385 <0 0 10 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
386 <0 0 11 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
387 <0 0 12 &gic 0 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
388 <0 0 13 &gic 0 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
389 <0 0 14 &gic 0 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
390 <0 0 15 &gic 0 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
391 <0 0 16 &gic 0 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
392 <0 0 17 &gic 0 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
393 <0 0 18 &gic 0 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
394 <0 0 19 &gic 0 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
395 <0 0 20 &gic 0 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
396 <0 0 21 &gic 0 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
397 <0 0 22 &gic 0 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
398 <0 0 23 &gic 0 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
399 <0 0 24 &gic 0 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
400 <0 0 25 &gic 0 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
401 <0 0 26 &gic 0 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
402 <0 0 27 &gic 0 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
403 <0 0 28 &gic 0 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
404 <0 0 29 &gic 0 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
405 <0 0 30 &gic 0 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
406 <0 0 31 &gic 0 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
407 <0 0 32 &gic 0 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
408 <0 0 33 &gic 0 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
409 <0 0 34 &gic 0 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
410 <0 0 35 &gic 0 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
411 <0 0 36 &gic 0 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
412 <0 0 37 &gic 0 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
413 <0 0 38 &gic 0 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
414 <0 0 39 &gic 0 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
415 <0 0 40 &gic 0 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
416 <0 0 41 &gic 0 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
417 <0 0 42 &gic 0 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
418 <0 0 43 &gic 0 0 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
419 <0 0 44 &gic 0 0 GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
420 <0 0 46 &gic 0 0 GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;