Lines Matching +full:t8103 +full:- +full:fpwm
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
14 #include <dt-bindings/spmi/spmi.h>
17 compatible = "apple,t8112", "apple,arm-platform";
19 #address-cells = <2>;
20 #size-cells = <2>;
23 #address-cells = <2>;
24 #size-cells = <0>;
26 cpu-map {
62 enable-method = "spin-table";
63 cpu-release-addr = <0 0>; /* To be filled by loader */
64 operating-points-v2 = <&ecluster_opp>;
65 capacity-dmips-mhz = <756>;
66 performance-domains = <&cpufreq_e>;
67 next-level-cache = <&l2_cache_0>;
68 i-cache-size = <0x20000>;
69 d-cache-size = <0x10000>;
76 enable-method = "spin-table";
77 cpu-release-addr = <0 0>; /* To be filled by loader */
78 operating-points-v2 = <&ecluster_opp>;
79 capacity-dmips-mhz = <756>;
80 performance-domains = <&cpufreq_e>;
81 next-level-cache = <&l2_cache_0>;
82 i-cache-size = <0x20000>;
83 d-cache-size = <0x10000>;
90 enable-method = "spin-table";
91 cpu-release-addr = <0 0>; /* To be filled by loader */
92 operating-points-v2 = <&ecluster_opp>;
93 capacity-dmips-mhz = <756>;
94 performance-domains = <&cpufreq_e>;
95 next-level-cache = <&l2_cache_0>;
96 i-cache-size = <0x20000>;
97 d-cache-size = <0x10000>;
104 enable-method = "spin-table";
105 cpu-release-addr = <0 0>; /* To be filled by loader */
106 operating-points-v2 = <&ecluster_opp>;
107 capacity-dmips-mhz = <756>;
108 performance-domains = <&cpufreq_e>;
109 next-level-cache = <&l2_cache_0>;
110 i-cache-size = <0x20000>;
111 d-cache-size = <0x10000>;
118 enable-method = "spin-table";
119 cpu-release-addr = <0 0>; /* To be filled by loader */
120 operating-points-v2 = <&pcluster_opp>;
121 capacity-dmips-mhz = <1024>;
122 performance-domains = <&cpufreq_p>;
123 next-level-cache = <&l2_cache_1>;
124 i-cache-size = <0x30000>;
125 d-cache-size = <0x20000>;
132 enable-method = "spin-table";
133 cpu-release-addr = <0 0>; /* To be filled by loader */
134 operating-points-v2 = <&pcluster_opp>;
135 capacity-dmips-mhz = <1024>;
136 performance-domains = <&cpufreq_p>;
137 next-level-cache = <&l2_cache_1>;
138 i-cache-size = <0x30000>;
139 d-cache-size = <0x20000>;
146 enable-method = "spin-table";
147 cpu-release-addr = <0 0>; /* To be filled by loader */
148 operating-points-v2 = <&pcluster_opp>;
149 capacity-dmips-mhz = <1024>;
150 performance-domains = <&cpufreq_p>;
151 next-level-cache = <&l2_cache_1>;
152 i-cache-size = <0x30000>;
153 d-cache-size = <0x20000>;
160 enable-method = "spin-table";
161 cpu-release-addr = <0 0>; /* To be filled by loader */
162 operating-points-v2 = <&pcluster_opp>;
163 capacity-dmips-mhz = <1024>;
164 performance-domains = <&cpufreq_p>;
165 next-level-cache = <&l2_cache_1>;
166 i-cache-size = <0x30000>;
167 d-cache-size = <0x20000>;
170 l2_cache_0: l2-cache-0 {
172 cache-level = <2>;
173 cache-unified;
174 cache-size = <0x400000>;
177 l2_cache_1: l2-cache-1 {
179 cache-level = <2>;
180 cache-unified;
181 cache-size = <0x1000000>;
185 ecluster_opp: opp-table-0 {
186 compatible = "operating-points-v2";
187 opp-shared;
190 opp-hz = /bits/ 64 <600000000>;
191 opp-level = <1>;
192 clock-latency-ns = <7500>;
195 opp-hz = /bits/ 64 <912000000>;
196 opp-level = <2>;
197 clock-latency-ns = <20000>;
200 opp-hz = /bits/ 64 <1284000000>;
201 opp-level = <3>;
202 clock-latency-ns = <22000>;
205 opp-hz = /bits/ 64 <1752000000>;
206 opp-level = <4>;
207 clock-latency-ns = <30000>;
210 opp-hz = /bits/ 64 <2004000000>;
211 opp-level = <5>;
212 clock-latency-ns = <35000>;
215 opp-hz = /bits/ 64 <2256000000>;
216 opp-level = <6>;
217 clock-latency-ns = <39000>;
220 opp-hz = /bits/ 64 <2424000000>;
221 opp-level = <7>;
222 clock-latency-ns = <53000>;
226 pcluster_opp: opp-table-1 {
227 compatible = "operating-points-v2";
228 opp-shared;
231 opp-hz = /bits/ 64 <660000000>;
232 opp-level = <1>;
233 clock-latency-ns = <9000>;
236 opp-hz = /bits/ 64 <924000000>;
237 opp-level = <2>;
238 clock-latency-ns = <19000>;
241 opp-hz = /bits/ 64 <1188000000>;
242 opp-level = <3>;
243 clock-latency-ns = <22000>;
246 opp-hz = /bits/ 64 <1452000000>;
247 opp-level = <4>;
248 clock-latency-ns = <24000>;
251 opp-hz = /bits/ 64 <1704000000>;
252 opp-level = <5>;
253 clock-latency-ns = <26000>;
256 opp-hz = /bits/ 64 <1968000000>;
257 opp-level = <6>;
258 clock-latency-ns = <28000>;
261 opp-hz = /bits/ 64 <2208000000>;
262 opp-level = <7>;
263 clock-latency-ns = <30000>;
266 opp-hz = /bits/ 64 <2400000000>;
267 opp-level = <8>;
268 clock-latency-ns = <33000>;
271 opp-hz = /bits/ 64 <2568000000>;
272 opp-level = <9>;
273 clock-latency-ns = <34000>;
276 opp-hz = /bits/ 64 <2724000000>;
277 opp-level = <10>;
278 clock-latency-ns = <36000>;
281 opp-hz = /bits/ 64 <2868000000>;
282 opp-level = <11>;
283 clock-latency-ns = <41000>;
286 opp-hz = /bits/ 64 <2988000000>;
287 opp-level = <12>;
288 clock-latency-ns = <42000>;
291 opp-hz = /bits/ 64 <3096000000>;
292 opp-level = <13>;
293 clock-latency-ns = <44000>;
296 opp-hz = /bits/ 64 <3204000000>;
297 opp-level = <14>;
298 clock-latency-ns = <46000>;
303 opp-hz = /bits/ 64 <3324000000>;
304 opp-level = <15>;
305 clock-latency-ns = <62000>;
306 turbo-mode;
309 opp-hz = /bits/ 64 <3408000000>;
310 opp-level = <16>;
311 clock-latency-ns = <62000>;
312 turbo-mode;
315 opp-hz = /bits/ 64 <3504000000>;
316 opp-level = <17>;
317 clock-latency-ns = <62000>;
318 turbo-mode;
324 compatible = "arm,armv8-timer";
325 interrupt-parent = <&aic>;
326 interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt";
333 pmu-e {
334 compatible = "apple,blizzard-pmu";
335 interrupt-parent = <&aic>;
339 pmu-p {
340 compatible = "apple,avalanche-pmu";
341 interrupt-parent = <&aic>;
345 clkref: clock-ref {
346 compatible = "fixed-clock";
347 #clock-cells = <0>;
348 clock-frequency = <24000000>;
349 clock-output-names = "clkref";
352 clk_200m: clock-200m {
353 compatible = "fixed-clock";
354 #clock-cells = <0>;
355 clock-frequency = <200000000>;
356 clock-output-names = "clk_200m";
363 nco_clkref: clock-ref-nco {
364 compatible = "fixed-clock";
365 #clock-cells = <0>;
366 clock-output-names = "nco_ref";
370 compatible = "simple-bus";
371 #address-cells = <2>;
372 #size-cells = <2>;
375 nonposted-mmio;
378 compatible = "apple,t8112-cluster-cpufreq", "apple,cluster-cpufreq";
380 #performance-domain-cells = <0>;
384 compatible = "apple,t8112-cluster-cpufreq", "apple,cluster-cpufreq";
386 #performance-domain-cells = <0>;
389 display_dfr: display-pipe@228200000 {
390 compatible = "apple,t8112-display-pipe", "apple,h7-display-pipe";
393 reg-names = "be", "fe";
394 power-domains = <&ps_dispdfr_fe>, <&ps_dispdfr_be>;
395 interrupt-parent = <&aic>;
398 interrupt-names = "be", "fe";
404 remote-endpoint = <&dfr_mipi_in_adp>;
410 compatible = "apple,t8110-dart";
412 interrupt-parent = <&aic>;
414 #iommu-cells = <1>;
415 power-domains = <&ps_dispdfr_fe>;
420 compatible = "apple,t8112-display-pipe-mipi", "apple,h7-display-pipe-mipi";
422 power-domains = <&ps_mipi_dsi>;
423 #address-cells = <1>;
424 #size-cells = <0>;
428 #address-cells = <1>;
429 #size-cells = <0>;
433 #address-cells = <1>;
434 #size-cells = <0>;
438 remote-endpoint = <&dfr_adp_out_mipi>;
444 #address-cells = <1>;
445 #size-cells = <0>;
451 compatible = "apple,t8110-dart";
453 interrupt-parent = <&aic>;
455 #iommu-cells = <1>;
456 power-domains = <&ps_sio_cpu>;
460 compatible = "apple,t8112-i2c", "apple,i2c";
463 interrupt-parent = <&aic>;
465 pinctrl-0 = <&i2c0_pins>;
466 pinctrl-names = "default";
467 #address-cells = <0x1>;
468 #size-cells = <0x0>;
469 power-domains = <&ps_i2c0>;
474 compatible = "apple,t8112-i2c", "apple,i2c";
477 interrupt-parent = <&aic>;
479 pinctrl-0 = <&i2c1_pins>;
480 pinctrl-names = "default";
481 #address-cells = <0x1>;
482 #size-cells = <0x0>;
483 power-domains = <&ps_i2c1>;
488 compatible = "apple,t8112-i2c", "apple,i2c";
491 interrupt-parent = <&aic>;
493 pinctrl-0 = <&i2c2_pins>;
494 pinctrl-names = "default";
495 #address-cells = <0x1>;
496 #size-cells = <0x0>;
497 power-domains = <&ps_i2c2>;
502 compatible = "apple,t8112-i2c", "apple,i2c";
505 interrupt-parent = <&aic>;
507 pinctrl-0 = <&i2c3_pins>;
508 pinctrl-names = "default";
509 #address-cells = <0x1>;
510 #size-cells = <0x0>;
511 power-domains = <&ps_i2c3>;
516 compatible = "apple,t8112-i2c", "apple,i2c";
519 interrupt-parent = <&aic>;
521 pinctrl-0 = <&i2c4_pins>;
522 pinctrl-names = "default";
523 #address-cells = <0x1>;
524 #size-cells = <0x0>;
525 power-domains = <&ps_i2c4>;
530 compatible = "apple,t8112-fpwm", "apple,s5l-fpwm";
532 power-domains = <&ps_fpwm1>;
534 #pwm-cells = <2>;
539 compatible = "apple,t8112-spi", "apple,spi";
541 interrupt-parent = <&aic>;
544 pinctrl-0 = <&spi1_pins>;
545 pinctrl-names = "default";
546 power-domains = <&ps_spi1>;
547 #address-cells = <1>;
548 #size-cells = <0>;
553 compatible = "apple,t8112-spi", "apple,spi";
555 interrupt-parent = <&aic>;
558 pinctrl-0 = <&spi3_pins>;
559 pinctrl-names = "default";
560 power-domains = <&ps_spi3>;
561 #address-cells = <1>;
562 #size-cells = <0>;
567 compatible = "apple,s5l-uart";
569 reg-io-width = <4>;
570 interrupt-parent = <&aic>;
577 clock-names = "uart", "clk_uart_baud0";
578 power-domains = <&ps_uart0>;
583 compatible = "apple,s5l-uart";
585 reg-io-width = <4>;
586 interrupt-parent = <&aic>;
589 clock-names = "uart", "clk_uart_baud0";
590 power-domains = <&ps_uart2>;
594 admac: dma-controller@238200000 {
595 compatible = "apple,t8112-admac", "apple,admac";
597 dma-channels = <24>;
598 interrupts-extended = <0>,
602 #dma-cells = <1>;
604 power-domains = <&ps_sio_adma>;
609 compatible = "apple,t8112-mca", "apple,mca";
613 interrupt-parent = <&aic>;
624 power-domains = <&ps_audio_p>, <&ps_mca0>, <&ps_mca1>,
632 dma-names = "tx0a", "rx0a", "tx0b", "rx0b",
639 #sound-dai-cells = <1>;
642 nco: clock-controller@23b044000 {
643 compatible = "apple,t8112-nco", "apple,nco";
646 #clock-cells = <1>;
649 aic: interrupt-controller@23b0c0000 {
650 compatible = "apple,t8112-aic", "apple,aic2";
651 #interrupt-cells = <3>;
652 interrupt-controller;
655 reg-names = "core", "event";
656 power-domains = <&ps_aic>;
659 e-core-pmu-affinity {
660 apple,fiq-index = <AIC_CPU_PMU_E>;
664 p-core-pmu-affinity {
665 apple,fiq-index = <AIC_CPU_PMU_P>;
671 pmgr: power-management@23b700000 {
672 compatible = "apple,t8112-pmgr", "apple,pmgr", "syscon", "simple-mfd";
673 #address-cells = <1>;
674 #size-cells = <1>;
676 /* child nodes are added in t8103-pmgr.dtsi */
680 compatible = "apple,t8112-pinctrl", "apple,pinctrl";
682 power-domains = <&ps_gpio>;
684 gpio-controller;
685 #gpio-cells = <2>;
686 gpio-ranges = <&pinctrl_ap 0 0 213>;
689 interrupt-controller;
690 #interrupt-cells = <2>;
691 interrupt-parent = <&aic>;
700 i2c0_pins: i2c0-pins {
705 i2c1_pins: i2c1-pins {
710 i2c2_pins: i2c2-pins {
715 i2c3_pins: i2c3-pins {
720 i2c4_pins: i2c4-pins {
725 spi1_pins: spi1-pins {
732 spi3_pins: spi3-pins {
739 pcie_pins: pcie-pins {
748 compatible = "apple,t8112-pinctrl", "apple,pinctrl";
750 power-domains = <&ps_nub_gpio>;
752 gpio-controller;
753 #gpio-cells = <2>;
754 gpio-ranges = <&pinctrl_nub 0 0 24>;
757 interrupt-controller;
758 #interrupt-cells = <2>;
759 interrupt-parent = <&aic>;
769 pmgr_mini: power-management@23d280000 {
770 compatible = "apple,t8112-pmgr", "apple,pmgr", "syscon", "simple-mfd";
771 #address-cells = <1>;
772 #size-cells = <1>;
774 /* child nodes are added in t8103-pmgr.dtsi */
778 compatible = "apple,t8112-wdt", "apple,wdt";
781 interrupt-parent = <&aic>;
786 compatible = "apple,t8112-pinctrl", "apple,pinctrl";
789 gpio-controller;
790 #gpio-cells = <2>;
791 gpio-ranges = <&pinctrl_smc 0 0 18>;
794 interrupt-controller;
795 #interrupt-cells = <2>;
796 interrupt-parent = <&aic>;
807 compatible = "apple,t8112-pinctrl", "apple,pinctrl";
810 gpio-controller;
811 #gpio-cells = <2>;
812 gpio-ranges = <&pinctrl_aop 0 0 54>;
815 interrupt-controller;
816 #interrupt-cells = <2>;
817 interrupt-parent = <&aic>;
828 compatible = "apple,t8112-asc-mailbox", "apple,asc-mailbox-v4";
830 interrupt-parent = <&aic>;
835 interrupt-names = "send-empty", "send-not-empty",
836 "recv-empty", "recv-not-empty";
837 #mbox-cells = <0>;
838 power-domains = <&ps_ans>;
842 compatible = "apple,t8112-sart", "apple,t6000-sart";
844 power-domains = <&ps_ans>;
848 compatible = "apple,t8112-nvme-ans2", "apple,nvme-ans2";
851 reg-names = "nvme", "ans";
852 interrupt-parent = <&aic>;
856 power-domains = <&ps_ans>, <&ps_apcie_st>;
857 power-domain-names = "ans", "apcie0";
862 compatible = "apple,t8110-dart";
864 #iommu-cells = <1>;
865 interrupt-parent = <&aic>;
867 power-domains = <&ps_apcie_gp>;
871 compatible = "apple,t8110-dart";
873 #iommu-cells = <1>;
874 interrupt-parent = <&aic>;
876 power-domains = <&ps_apcie_gp>;
881 compatible = "apple,t8110-dart";
883 #iommu-cells = <1>;
884 interrupt-parent = <&aic>;
886 power-domains = <&ps_apcie_gp>;
891 compatible = "apple,t8110-dart";
893 #iommu-cells = <1>;
894 interrupt-parent = <&aic>;
896 power-domains = <&ps_apcie_gp>;
901 compatible = "apple,t8112-pcie", "apple,pcie";
910 reg-names = "config", "rc", "port0", "port1", "port2", "port3";
912 interrupt-parent = <&aic>;
918 msi-controller;
919 msi-parent = <&pcie0>;
920 msi-ranges = <&aic AIC_IRQ 793 IRQ_TYPE_EDGE_RISING 32>;
922 iommu-map = <0x100 &pcie0_dart 0 1>,
926 iommu-map-mask = <0xff00>;
928 bus-range = <0 4>;
929 #address-cells = <3>;
930 #size-cells = <2>;
934 power-domains = <&ps_apcie_gp>;
935 pinctrl-0 = <&pcie_pins>;
936 pinctrl-names = "default";
941 reset-gpios = <&pinctrl_ap 166 GPIO_ACTIVE_LOW>;
943 #address-cells = <3>;
944 #size-cells = <2>;
947 interrupt-controller;
948 #interrupt-cells = <1>;
950 interrupt-map-mask = <0 0 0 7>;
951 interrupt-map = <0 0 0 1 &port00 0 0 0 0>,
960 reset-gpios = <&pinctrl_ap 167 GPIO_ACTIVE_LOW>;
962 #address-cells = <3>;
963 #size-cells = <2>;
966 interrupt-controller;
967 #interrupt-cells = <1>;
969 interrupt-map-mask = <0 0 0 7>;
970 interrupt-map = <0 0 0 1 &port01 0 0 0 0>,
981 reset-gpios = <&pinctrl_ap 168 GPIO_ACTIVE_LOW>;
983 #address-cells = <3>;
984 #size-cells = <2>;
987 interrupt-controller;
988 #interrupt-cells = <1>;
990 interrupt-map-mask = <0 0 0 7>;
991 interrupt-map = <0 0 0 1 &port02 0 0 0 0>,
1003 //reset-gpios = <&pinctrl_ap 33 GPIO_ACTIVE_LOW>;
1005 #address-cells = <3>;
1006 #size-cells = <2>;
1009 interrupt-controller;
1010 #interrupt-cells = <1>;
1012 interrupt-map-mask = <0 0 0 7>;
1013 interrupt-map = <0 0 0 1 &port03 0 0 0 0>,
1024 #include "t8112-pmgr.dtsi"