Lines Matching +full:t6000 +full:- +full:aic
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
14 #include <dt-bindings/spmi/spmi.h>
17 compatible = "apple,t8112", "apple,arm-platform";
19 #address-cells = <2>;
20 #size-cells = <2>;
23 #address-cells = <2>;
24 #size-cells = <0>;
26 cpu-map {
62 enable-method = "spin-table";
63 cpu-release-addr = <0 0>; /* To be filled by loader */
64 operating-points-v2 = <&ecluster_opp>;
65 capacity-dmips-mhz = <756>;
66 performance-domains = <&cpufreq_e>;
67 next-level-cache = <&l2_cache_0>;
68 i-cache-size = <0x20000>;
69 d-cache-size = <0x10000>;
76 enable-method = "spin-table";
77 cpu-release-addr = <0 0>; /* To be filled by loader */
78 operating-points-v2 = <&ecluster_opp>;
79 capacity-dmips-mhz = <756>;
80 performance-domains = <&cpufreq_e>;
81 next-level-cache = <&l2_cache_0>;
82 i-cache-size = <0x20000>;
83 d-cache-size = <0x10000>;
90 enable-method = "spin-table";
91 cpu-release-addr = <0 0>; /* To be filled by loader */
92 operating-points-v2 = <&ecluster_opp>;
93 capacity-dmips-mhz = <756>;
94 performance-domains = <&cpufreq_e>;
95 next-level-cache = <&l2_cache_0>;
96 i-cache-size = <0x20000>;
97 d-cache-size = <0x10000>;
104 enable-method = "spin-table";
105 cpu-release-addr = <0 0>; /* To be filled by loader */
106 operating-points-v2 = <&ecluster_opp>;
107 capacity-dmips-mhz = <756>;
108 performance-domains = <&cpufreq_e>;
109 next-level-cache = <&l2_cache_0>;
110 i-cache-size = <0x20000>;
111 d-cache-size = <0x10000>;
118 enable-method = "spin-table";
119 cpu-release-addr = <0 0>; /* To be filled by loader */
120 operating-points-v2 = <&pcluster_opp>;
121 capacity-dmips-mhz = <1024>;
122 performance-domains = <&cpufreq_p>;
123 next-level-cache = <&l2_cache_1>;
124 i-cache-size = <0x30000>;
125 d-cache-size = <0x20000>;
132 enable-method = "spin-table";
133 cpu-release-addr = <0 0>; /* To be filled by loader */
134 operating-points-v2 = <&pcluster_opp>;
135 capacity-dmips-mhz = <1024>;
136 performance-domains = <&cpufreq_p>;
137 next-level-cache = <&l2_cache_1>;
138 i-cache-size = <0x30000>;
139 d-cache-size = <0x20000>;
146 enable-method = "spin-table";
147 cpu-release-addr = <0 0>; /* To be filled by loader */
148 operating-points-v2 = <&pcluster_opp>;
149 capacity-dmips-mhz = <1024>;
150 performance-domains = <&cpufreq_p>;
151 next-level-cache = <&l2_cache_1>;
152 i-cache-size = <0x30000>;
153 d-cache-size = <0x20000>;
160 enable-method = "spin-table";
161 cpu-release-addr = <0 0>; /* To be filled by loader */
162 operating-points-v2 = <&pcluster_opp>;
163 capacity-dmips-mhz = <1024>;
164 performance-domains = <&cpufreq_p>;
165 next-level-cache = <&l2_cache_1>;
166 i-cache-size = <0x30000>;
167 d-cache-size = <0x20000>;
170 l2_cache_0: l2-cache-0 {
172 cache-level = <2>;
173 cache-unified;
174 cache-size = <0x400000>;
177 l2_cache_1: l2-cache-1 {
179 cache-level = <2>;
180 cache-unified;
181 cache-size = <0x1000000>;
185 ecluster_opp: opp-table-0 {
186 compatible = "operating-points-v2";
187 opp-shared;
190 opp-hz = /bits/ 64 <600000000>;
191 opp-level = <1>;
192 clock-latency-ns = <7500>;
195 opp-hz = /bits/ 64 <912000000>;
196 opp-level = <2>;
197 clock-latency-ns = <20000>;
200 opp-hz = /bits/ 64 <1284000000>;
201 opp-level = <3>;
202 clock-latency-ns = <22000>;
205 opp-hz = /bits/ 64 <1752000000>;
206 opp-level = <4>;
207 clock-latency-ns = <30000>;
210 opp-hz = /bits/ 64 <2004000000>;
211 opp-level = <5>;
212 clock-latency-ns = <35000>;
215 opp-hz = /bits/ 64 <2256000000>;
216 opp-level = <6>;
217 clock-latency-ns = <39000>;
220 opp-hz = /bits/ 64 <2424000000>;
221 opp-level = <7>;
222 clock-latency-ns = <53000>;
226 pcluster_opp: opp-table-1 {
227 compatible = "operating-points-v2";
228 opp-shared;
231 opp-hz = /bits/ 64 <660000000>;
232 opp-level = <1>;
233 clock-latency-ns = <9000>;
236 opp-hz = /bits/ 64 <924000000>;
237 opp-level = <2>;
238 clock-latency-ns = <19000>;
241 opp-hz = /bits/ 64 <1188000000>;
242 opp-level = <3>;
243 clock-latency-ns = <22000>;
246 opp-hz = /bits/ 64 <1452000000>;
247 opp-level = <4>;
248 clock-latency-ns = <24000>;
251 opp-hz = /bits/ 64 <1704000000>;
252 opp-level = <5>;
253 clock-latency-ns = <26000>;
256 opp-hz = /bits/ 64 <1968000000>;
257 opp-level = <6>;
258 clock-latency-ns = <28000>;
261 opp-hz = /bits/ 64 <2208000000>;
262 opp-level = <7>;
263 clock-latency-ns = <30000>;
266 opp-hz = /bits/ 64 <2400000000>;
267 opp-level = <8>;
268 clock-latency-ns = <33000>;
271 opp-hz = /bits/ 64 <2568000000>;
272 opp-level = <9>;
273 clock-latency-ns = <34000>;
276 opp-hz = /bits/ 64 <2724000000>;
277 opp-level = <10>;
278 clock-latency-ns = <36000>;
281 opp-hz = /bits/ 64 <2868000000>;
282 opp-level = <11>;
283 clock-latency-ns = <41000>;
286 opp-hz = /bits/ 64 <2988000000>;
287 opp-level = <12>;
288 clock-latency-ns = <42000>;
291 opp-hz = /bits/ 64 <3096000000>;
292 opp-level = <13>;
293 clock-latency-ns = <44000>;
296 opp-hz = /bits/ 64 <3204000000>;
297 opp-level = <14>;
298 clock-latency-ns = <46000>;
303 opp-hz = /bits/ 64 <3324000000>;
304 opp-level = <15>;
305 clock-latency-ns = <62000>;
306 turbo-mode;
309 opp-hz = /bits/ 64 <3408000000>;
310 opp-level = <16>;
311 clock-latency-ns = <62000>;
312 turbo-mode;
315 opp-hz = /bits/ 64 <3504000000>;
316 opp-level = <17>;
317 clock-latency-ns = <62000>;
318 turbo-mode;
324 compatible = "arm,armv8-timer";
325 interrupt-parent = <&aic>;
326 interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt";
333 pmu-e {
334 compatible = "apple,blizzard-pmu";
335 interrupt-parent = <&aic>;
339 pmu-p {
340 compatible = "apple,avalanche-pmu";
341 interrupt-parent = <&aic>;
345 clkref: clock-ref {
346 compatible = "fixed-clock";
347 #clock-cells = <0>;
348 clock-frequency = <24000000>;
349 clock-output-names = "clkref";
356 nco_clkref: clock-ref-nco {
357 compatible = "fixed-clock";
358 #clock-cells = <0>;
359 clock-output-names = "nco_ref";
363 compatible = "simple-bus";
364 #address-cells = <2>;
365 #size-cells = <2>;
368 nonposted-mmio;
371 compatible = "apple,t8112-cluster-cpufreq", "apple,cluster-cpufreq";
373 #performance-domain-cells = <0>;
377 compatible = "apple,t8112-cluster-cpufreq", "apple,cluster-cpufreq";
379 #performance-domain-cells = <0>;
383 compatible = "apple,t8110-dart";
385 interrupt-parent = <&aic>;
387 #iommu-cells = <1>;
388 power-domains = <&ps_sio_cpu>;
392 compatible = "apple,t8112-i2c", "apple,i2c";
395 interrupt-parent = <&aic>;
397 pinctrl-0 = <&i2c0_pins>;
398 pinctrl-names = "default";
399 #address-cells = <0x1>;
400 #size-cells = <0x0>;
401 power-domains = <&ps_i2c0>;
406 compatible = "apple,t8112-i2c", "apple,i2c";
409 interrupt-parent = <&aic>;
411 pinctrl-0 = <&i2c1_pins>;
412 pinctrl-names = "default";
413 #address-cells = <0x1>;
414 #size-cells = <0x0>;
415 power-domains = <&ps_i2c1>;
420 compatible = "apple,t8112-i2c", "apple,i2c";
423 interrupt-parent = <&aic>;
425 pinctrl-0 = <&i2c2_pins>;
426 pinctrl-names = "default";
427 #address-cells = <0x1>;
428 #size-cells = <0x0>;
429 power-domains = <&ps_i2c2>;
434 compatible = "apple,t8112-i2c", "apple,i2c";
437 interrupt-parent = <&aic>;
439 pinctrl-0 = <&i2c3_pins>;
440 pinctrl-names = "default";
441 #address-cells = <0x1>;
442 #size-cells = <0x0>;
443 power-domains = <&ps_i2c3>;
448 compatible = "apple,t8112-i2c", "apple,i2c";
451 interrupt-parent = <&aic>;
453 pinctrl-0 = <&i2c4_pins>;
454 pinctrl-names = "default";
455 #address-cells = <0x1>;
456 #size-cells = <0x0>;
457 power-domains = <&ps_i2c4>;
462 compatible = "apple,t8112-fpwm", "apple,s5l-fpwm";
464 power-domains = <&ps_fpwm1>;
466 #pwm-cells = <2>;
471 compatible = "apple,s5l-uart";
473 reg-io-width = <4>;
474 interrupt-parent = <&aic>;
481 clock-names = "uart", "clk_uart_baud0";
482 power-domains = <&ps_uart0>;
487 compatible = "apple,s5l-uart";
489 reg-io-width = <4>;
490 interrupt-parent = <&aic>;
493 clock-names = "uart", "clk_uart_baud0";
494 power-domains = <&ps_uart2>;
498 admac: dma-controller@238200000 {
499 compatible = "apple,t8112-admac", "apple,admac";
501 dma-channels = <24>;
502 interrupts-extended = <0>,
503 <&aic AIC_IRQ 760 IRQ_TYPE_LEVEL_HIGH>,
506 #dma-cells = <1>;
508 power-domains = <&ps_sio_adma>;
513 compatible = "apple,t8112-mca", "apple,mca";
517 interrupt-parent = <&aic>;
528 power-domains = <&ps_audio_p>, <&ps_mca0>, <&ps_mca1>,
536 dma-names = "tx0a", "rx0a", "tx0b", "rx0b",
543 #sound-dai-cells = <1>;
546 nco: clock-controller@23b044000 {
547 compatible = "apple,t8112-nco", "apple,nco";
550 #clock-cells = <1>;
553 aic: interrupt-controller@23b0c0000 { label
554 compatible = "apple,t8112-aic", "apple,aic2";
555 #interrupt-cells = <3>;
556 interrupt-controller;
559 reg-names = "core", "event";
560 power-domains = <&ps_aic>;
563 e-core-pmu-affinity {
564 apple,fiq-index = <AIC_CPU_PMU_E>;
568 p-core-pmu-affinity {
569 apple,fiq-index = <AIC_CPU_PMU_P>;
575 pmgr: power-management@23b700000 {
576 compatible = "apple,t8112-pmgr", "apple,pmgr", "syscon", "simple-mfd";
577 #address-cells = <1>;
578 #size-cells = <1>;
580 /* child nodes are added in t8103-pmgr.dtsi */
584 compatible = "apple,t8112-pinctrl", "apple,pinctrl";
586 power-domains = <&ps_gpio>;
588 gpio-controller;
589 #gpio-cells = <2>;
590 gpio-ranges = <&pinctrl_ap 0 0 213>;
593 interrupt-controller;
594 #interrupt-cells = <2>;
595 interrupt-parent = <&aic>;
604 i2c0_pins: i2c0-pins {
609 i2c1_pins: i2c1-pins {
614 i2c2_pins: i2c2-pins {
619 i2c3_pins: i2c3-pins {
624 i2c4_pins: i2c4-pins {
629 spi3_pins: spi3-pins {
636 pcie_pins: pcie-pins {
645 compatible = "apple,t8112-pinctrl", "apple,pinctrl";
647 power-domains = <&ps_nub_gpio>;
649 gpio-controller;
650 #gpio-cells = <2>;
651 gpio-ranges = <&pinctrl_nub 0 0 24>;
654 interrupt-controller;
655 #interrupt-cells = <2>;
656 interrupt-parent = <&aic>;
666 pmgr_mini: power-management@23d280000 {
667 compatible = "apple,t8112-pmgr", "apple,pmgr", "syscon", "simple-mfd";
668 #address-cells = <1>;
669 #size-cells = <1>;
671 /* child nodes are added in t8103-pmgr.dtsi */
675 compatible = "apple,t8112-wdt", "apple,wdt";
678 interrupt-parent = <&aic>;
683 compatible = "apple,t8112-pinctrl", "apple,pinctrl";
686 gpio-controller;
687 #gpio-cells = <2>;
688 gpio-ranges = <&pinctrl_smc 0 0 18>;
691 interrupt-controller;
692 #interrupt-cells = <2>;
693 interrupt-parent = <&aic>;
704 compatible = "apple,t8112-pinctrl", "apple,pinctrl";
707 gpio-controller;
708 #gpio-cells = <2>;
709 gpio-ranges = <&pinctrl_aop 0 0 54>;
712 interrupt-controller;
713 #interrupt-cells = <2>;
714 interrupt-parent = <&aic>;
725 compatible = "apple,t8112-asc-mailbox", "apple,asc-mailbox-v4";
727 interrupt-parent = <&aic>;
732 interrupt-names = "send-empty", "send-not-empty",
733 "recv-empty", "recv-not-empty";
734 #mbox-cells = <0>;
735 power-domains = <&ps_ans>;
739 compatible = "apple,t8112-sart", "apple,t6000-sart";
741 power-domains = <&ps_ans>;
745 compatible = "apple,t8112-nvme-ans2", "apple,nvme-ans2";
748 reg-names = "nvme", "ans";
749 interrupt-parent = <&aic>;
753 power-domains = <&ps_ans>, <&ps_apcie_st>;
754 power-domain-names = "ans", "apcie0";
759 compatible = "apple,t8110-dart";
761 #iommu-cells = <1>;
762 interrupt-parent = <&aic>;
764 power-domains = <&ps_apcie_gp>;
768 compatible = "apple,t8110-dart";
770 #iommu-cells = <1>;
771 interrupt-parent = <&aic>;
773 power-domains = <&ps_apcie_gp>;
778 compatible = "apple,t8110-dart";
780 #iommu-cells = <1>;
781 interrupt-parent = <&aic>;
783 power-domains = <&ps_apcie_gp>;
788 compatible = "apple,t8110-dart";
790 #iommu-cells = <1>;
791 interrupt-parent = <&aic>;
793 power-domains = <&ps_apcie_gp>;
798 compatible = "apple,t8112-pcie", "apple,pcie";
807 reg-names = "config", "rc", "port0", "port1", "port2", "port3";
809 interrupt-parent = <&aic>;
815 msi-controller;
816 msi-parent = <&pcie0>;
817 msi-ranges = <&aic AIC_IRQ 793 IRQ_TYPE_EDGE_RISING 32>;
819 iommu-map = <0x100 &pcie0_dart 0 1>,
823 iommu-map-mask = <0xff00>;
825 bus-range = <0 4>;
826 #address-cells = <3>;
827 #size-cells = <2>;
831 power-domains = <&ps_apcie_gp>;
832 pinctrl-0 = <&pcie_pins>;
833 pinctrl-names = "default";
838 reset-gpios = <&pinctrl_ap 166 GPIO_ACTIVE_LOW>;
840 #address-cells = <3>;
841 #size-cells = <2>;
844 interrupt-controller;
845 #interrupt-cells = <1>;
847 interrupt-map-mask = <0 0 0 7>;
848 interrupt-map = <0 0 0 1 &port00 0 0 0 0>,
857 reset-gpios = <&pinctrl_ap 167 GPIO_ACTIVE_LOW>;
859 #address-cells = <3>;
860 #size-cells = <2>;
863 interrupt-controller;
864 #interrupt-cells = <1>;
866 interrupt-map-mask = <0 0 0 7>;
867 interrupt-map = <0 0 0 1 &port01 0 0 0 0>,
878 reset-gpios = <&pinctrl_ap 168 GPIO_ACTIVE_LOW>;
880 #address-cells = <3>;
881 #size-cells = <2>;
884 interrupt-controller;
885 #interrupt-cells = <1>;
887 interrupt-map-mask = <0 0 0 7>;
888 interrupt-map = <0 0 0 1 &port02 0 0 0 0>,
900 //reset-gpios = <&pinctrl_ap 33 GPIO_ACTIVE_LOW>;
902 #address-cells = <3>;
903 #size-cells = <2>;
906 interrupt-controller;
907 #interrupt-cells = <1>;
909 interrupt-map-mask = <0 0 0 7>;
910 interrupt-map = <0 0 0 1 &port03 0 0 0 0>,
921 #include "t8112-pmgr.dtsi"