Lines Matching +full:nvme +full:- +full:ans2
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
14 #include <dt-bindings/spmi/spmi.h>
17 compatible = "apple,t8112", "apple,arm-platform";
19 #address-cells = <2>;
20 #size-cells = <2>;
27 #address-cells = <2>;
28 #size-cells = <0>;
30 cpu-map {
66 enable-method = "spin-table";
67 cpu-release-addr = <0 0>; /* To be filled by loader */
68 operating-points-v2 = <&ecluster_opp>;
69 capacity-dmips-mhz = <756>;
70 performance-domains = <&cpufreq_e>;
71 next-level-cache = <&l2_cache_0>;
72 i-cache-size = <0x20000>;
73 d-cache-size = <0x10000>;
80 enable-method = "spin-table";
81 cpu-release-addr = <0 0>; /* To be filled by loader */
82 operating-points-v2 = <&ecluster_opp>;
83 capacity-dmips-mhz = <756>;
84 performance-domains = <&cpufreq_e>;
85 next-level-cache = <&l2_cache_0>;
86 i-cache-size = <0x20000>;
87 d-cache-size = <0x10000>;
94 enable-method = "spin-table";
95 cpu-release-addr = <0 0>; /* To be filled by loader */
96 operating-points-v2 = <&ecluster_opp>;
97 capacity-dmips-mhz = <756>;
98 performance-domains = <&cpufreq_e>;
99 next-level-cache = <&l2_cache_0>;
100 i-cache-size = <0x20000>;
101 d-cache-size = <0x10000>;
108 enable-method = "spin-table";
109 cpu-release-addr = <0 0>; /* To be filled by loader */
110 operating-points-v2 = <&ecluster_opp>;
111 capacity-dmips-mhz = <756>;
112 performance-domains = <&cpufreq_e>;
113 next-level-cache = <&l2_cache_0>;
114 i-cache-size = <0x20000>;
115 d-cache-size = <0x10000>;
122 enable-method = "spin-table";
123 cpu-release-addr = <0 0>; /* To be filled by loader */
124 operating-points-v2 = <&pcluster_opp>;
125 capacity-dmips-mhz = <1024>;
126 performance-domains = <&cpufreq_p>;
127 next-level-cache = <&l2_cache_1>;
128 i-cache-size = <0x30000>;
129 d-cache-size = <0x20000>;
136 enable-method = "spin-table";
137 cpu-release-addr = <0 0>; /* To be filled by loader */
138 operating-points-v2 = <&pcluster_opp>;
139 capacity-dmips-mhz = <1024>;
140 performance-domains = <&cpufreq_p>;
141 next-level-cache = <&l2_cache_1>;
142 i-cache-size = <0x30000>;
143 d-cache-size = <0x20000>;
150 enable-method = "spin-table";
151 cpu-release-addr = <0 0>; /* To be filled by loader */
152 operating-points-v2 = <&pcluster_opp>;
153 capacity-dmips-mhz = <1024>;
154 performance-domains = <&cpufreq_p>;
155 next-level-cache = <&l2_cache_1>;
156 i-cache-size = <0x30000>;
157 d-cache-size = <0x20000>;
164 enable-method = "spin-table";
165 cpu-release-addr = <0 0>; /* To be filled by loader */
166 operating-points-v2 = <&pcluster_opp>;
167 capacity-dmips-mhz = <1024>;
168 performance-domains = <&cpufreq_p>;
169 next-level-cache = <&l2_cache_1>;
170 i-cache-size = <0x30000>;
171 d-cache-size = <0x20000>;
174 l2_cache_0: l2-cache-0 {
176 cache-level = <2>;
177 cache-unified;
178 cache-size = <0x400000>;
181 l2_cache_1: l2-cache-1 {
183 cache-level = <2>;
184 cache-unified;
185 cache-size = <0x1000000>;
189 ecluster_opp: opp-table-0 {
190 compatible = "operating-points-v2";
191 opp-shared;
194 opp-hz = /bits/ 64 <600000000>;
195 opp-level = <1>;
196 clock-latency-ns = <7500>;
199 opp-hz = /bits/ 64 <912000000>;
200 opp-level = <2>;
201 clock-latency-ns = <20000>;
204 opp-hz = /bits/ 64 <1284000000>;
205 opp-level = <3>;
206 clock-latency-ns = <22000>;
209 opp-hz = /bits/ 64 <1752000000>;
210 opp-level = <4>;
211 clock-latency-ns = <30000>;
214 opp-hz = /bits/ 64 <2004000000>;
215 opp-level = <5>;
216 clock-latency-ns = <35000>;
219 opp-hz = /bits/ 64 <2256000000>;
220 opp-level = <6>;
221 clock-latency-ns = <39000>;
224 opp-hz = /bits/ 64 <2424000000>;
225 opp-level = <7>;
226 clock-latency-ns = <53000>;
230 pcluster_opp: opp-table-1 {
231 compatible = "operating-points-v2";
232 opp-shared;
235 opp-hz = /bits/ 64 <660000000>;
236 opp-level = <1>;
237 clock-latency-ns = <9000>;
240 opp-hz = /bits/ 64 <924000000>;
241 opp-level = <2>;
242 clock-latency-ns = <19000>;
245 opp-hz = /bits/ 64 <1188000000>;
246 opp-level = <3>;
247 clock-latency-ns = <22000>;
250 opp-hz = /bits/ 64 <1452000000>;
251 opp-level = <4>;
252 clock-latency-ns = <24000>;
255 opp-hz = /bits/ 64 <1704000000>;
256 opp-level = <5>;
257 clock-latency-ns = <26000>;
260 opp-hz = /bits/ 64 <1968000000>;
261 opp-level = <6>;
262 clock-latency-ns = <28000>;
265 opp-hz = /bits/ 64 <2208000000>;
266 opp-level = <7>;
267 clock-latency-ns = <30000>;
270 opp-hz = /bits/ 64 <2400000000>;
271 opp-level = <8>;
272 clock-latency-ns = <33000>;
275 opp-hz = /bits/ 64 <2568000000>;
276 opp-level = <9>;
277 clock-latency-ns = <34000>;
280 opp-hz = /bits/ 64 <2724000000>;
281 opp-level = <10>;
282 clock-latency-ns = <36000>;
285 opp-hz = /bits/ 64 <2868000000>;
286 opp-level = <11>;
287 clock-latency-ns = <41000>;
290 opp-hz = /bits/ 64 <2988000000>;
291 opp-level = <12>;
292 clock-latency-ns = <42000>;
295 opp-hz = /bits/ 64 <3096000000>;
296 opp-level = <13>;
297 clock-latency-ns = <44000>;
300 opp-hz = /bits/ 64 <3204000000>;
301 opp-level = <14>;
302 clock-latency-ns = <46000>;
307 opp-hz = /bits/ 64 <3324000000>;
308 opp-level = <15>;
309 clock-latency-ns = <62000>;
310 turbo-mode;
313 opp-hz = /bits/ 64 <3408000000>;
314 opp-level = <16>;
315 clock-latency-ns = <62000>;
316 turbo-mode;
319 opp-hz = /bits/ 64 <3504000000>;
320 opp-level = <17>;
321 clock-latency-ns = <62000>;
322 turbo-mode;
328 compatible = "arm,armv8-timer";
329 interrupt-parent = <&aic>;
330 interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt";
337 pmu-e {
338 compatible = "apple,blizzard-pmu";
339 interrupt-parent = <&aic>;
343 pmu-p {
344 compatible = "apple,avalanche-pmu";
345 interrupt-parent = <&aic>;
349 clkref: clock-ref {
350 compatible = "fixed-clock";
351 #clock-cells = <0>;
352 clock-frequency = <24000000>;
353 clock-output-names = "clkref";
356 clk_200m: clock-200m {
357 compatible = "fixed-clock";
358 #clock-cells = <0>;
359 clock-frequency = <200000000>;
360 clock-output-names = "clk_200m";
367 nco_clkref: clock-ref-nco {
368 compatible = "fixed-clock";
369 #clock-cells = <0>;
370 clock-output-names = "nco_ref";
373 reserved-memory {
374 #address-cells = <2>;
375 #size-cells = <2>;
382 gpu_hw_cal_a: hw-cal-a {
386 gpu_hw_cal_b: hw-cal-b {
390 uat_handoff: uat-handoff {
394 uat_pagetables: uat-pagetables {
398 uat_ttbs: uat-ttbs {
404 compatible = "simple-bus";
405 #address-cells = <2>;
406 #size-cells = <2>;
409 nonposted-mmio;
412 compatible = "apple,agx-g14g";
415 reg-names = "asc", "sgx";
417 power-domains = <&ps_gfx>;
418 memory-region = <&uat_ttbs>, <&uat_pagetables>, <&uat_handoff>,
420 memory-region-names = "ttbs", "pagetables", "handoff",
421 "hw-cal-a", "hw-cal-b", "globals";
423 apple,firmware-abi = <0 0 0>;
427 compatible = "apple,t8103-asc-mailbox", "apple,asc-mailbox-v4";
429 interrupt-parent = <&aic>;
434 interrupt-names = "send-empty", "send-not-empty",
435 "recv-empty", "recv-not-empty";
436 #mbox-cells = <0>;
440 compatible = "apple,t8112-cluster-cpufreq", "apple,cluster-cpufreq";
442 #performance-domain-cells = <0>;
446 compatible = "apple,t8112-cluster-cpufreq", "apple,cluster-cpufreq";
448 #performance-domain-cells = <0>;
451 display_dfr: display-pipe@228200000 {
452 compatible = "apple,t8112-display-pipe", "apple,h7-display-pipe";
455 reg-names = "be", "fe";
456 power-domains = <&ps_dispdfr_fe>, <&ps_dispdfr_be>;
457 interrupt-parent = <&aic>;
460 interrupt-names = "be", "fe";
466 remote-endpoint = <&dfr_mipi_in_adp>;
472 compatible = "apple,t8110-dart";
474 interrupt-parent = <&aic>;
476 #iommu-cells = <1>;
477 power-domains = <&ps_dispdfr_fe>;
482 compatible = "apple,t8112-display-pipe-mipi", "apple,h7-display-pipe-mipi";
484 power-domains = <&ps_mipi_dsi>;
488 #address-cells = <1>;
489 #size-cells = <0>;
493 #address-cells = <1>;
494 #size-cells = <0>;
498 remote-endpoint = <&dfr_adp_out_mipi>;
504 #address-cells = <1>;
505 #size-cells = <0>;
511 compatible = "apple,t8110-dart";
513 interrupt-parent = <&aic>;
515 #iommu-cells = <1>;
516 power-domains = <&ps_sio_cpu>;
520 compatible = "apple,t8112-i2c", "apple,i2c";
523 interrupt-parent = <&aic>;
525 pinctrl-0 = <&i2c0_pins>;
526 pinctrl-names = "default";
527 #address-cells = <0x1>;
528 #size-cells = <0x0>;
529 power-domains = <&ps_i2c0>;
534 compatible = "apple,t8112-i2c", "apple,i2c";
537 interrupt-parent = <&aic>;
539 pinctrl-0 = <&i2c1_pins>;
540 pinctrl-names = "default";
541 #address-cells = <0x1>;
542 #size-cells = <0x0>;
543 power-domains = <&ps_i2c1>;
548 compatible = "apple,t8112-i2c", "apple,i2c";
551 interrupt-parent = <&aic>;
553 pinctrl-0 = <&i2c2_pins>;
554 pinctrl-names = "default";
555 #address-cells = <0x1>;
556 #size-cells = <0x0>;
557 power-domains = <&ps_i2c2>;
562 compatible = "apple,t8112-i2c", "apple,i2c";
565 interrupt-parent = <&aic>;
567 pinctrl-0 = <&i2c3_pins>;
568 pinctrl-names = "default";
569 #address-cells = <0x1>;
570 #size-cells = <0x0>;
571 power-domains = <&ps_i2c3>;
576 compatible = "apple,t8112-i2c", "apple,i2c";
579 interrupt-parent = <&aic>;
581 pinctrl-0 = <&i2c4_pins>;
582 pinctrl-names = "default";
583 #address-cells = <0x1>;
584 #size-cells = <0x0>;
585 power-domains = <&ps_i2c4>;
590 compatible = "apple,t8112-fpwm", "apple,s5l-fpwm";
592 power-domains = <&ps_fpwm1>;
594 #pwm-cells = <2>;
599 compatible = "apple,t8112-spi", "apple,spi";
601 interrupt-parent = <&aic>;
604 pinctrl-0 = <&spi1_pins>;
605 pinctrl-names = "default";
606 power-domains = <&ps_spi1>;
607 #address-cells = <1>;
608 #size-cells = <0>;
613 compatible = "apple,t8112-spi", "apple,spi";
615 interrupt-parent = <&aic>;
618 pinctrl-0 = <&spi3_pins>;
619 pinctrl-names = "default";
620 power-domains = <&ps_spi3>;
621 #address-cells = <1>;
622 #size-cells = <0>;
627 compatible = "apple,s5l-uart";
629 reg-io-width = <4>;
630 interrupt-parent = <&aic>;
637 clock-names = "uart", "clk_uart_baud0";
638 power-domains = <&ps_uart0>;
643 compatible = "apple,s5l-uart";
645 reg-io-width = <4>;
646 interrupt-parent = <&aic>;
649 clock-names = "uart", "clk_uart_baud0";
650 power-domains = <&ps_uart2>;
654 admac: dma-controller@238200000 {
655 compatible = "apple,t8112-admac", "apple,admac";
657 dma-channels = <24>;
658 interrupts-extended = <0>,
662 #dma-cells = <1>;
664 power-domains = <&ps_sio_adma>;
669 compatible = "apple,t8112-mca", "apple,mca";
673 interrupt-parent = <&aic>;
684 power-domains = <&ps_audio_p>, <&ps_mca0>, <&ps_mca1>,
692 dma-names = "tx0a", "rx0a", "tx0b", "rx0b",
699 #sound-dai-cells = <1>;
702 nco: clock-controller@23b044000 {
703 compatible = "apple,t8112-nco", "apple,nco";
706 #clock-cells = <1>;
709 aic: interrupt-controller@23b0c0000 {
710 compatible = "apple,t8112-aic", "apple,aic2";
711 #interrupt-cells = <3>;
712 interrupt-controller;
715 reg-names = "core", "event";
716 power-domains = <&ps_aic>;
719 e-core-pmu-affinity {
720 apple,fiq-index = <AIC_CPU_PMU_E>;
724 p-core-pmu-affinity {
725 apple,fiq-index = <AIC_CPU_PMU_P>;
731 pmgr: power-management@23b700000 {
732 compatible = "apple,t8112-pmgr", "apple,pmgr", "syscon", "simple-mfd";
733 #address-cells = <1>;
734 #size-cells = <1>;
736 /* child nodes are added in t8103-pmgr.dtsi */
740 compatible = "apple,t8112-pinctrl", "apple,pinctrl";
742 power-domains = <&ps_gpio>;
744 gpio-controller;
745 #gpio-cells = <2>;
746 gpio-ranges = <&pinctrl_ap 0 0 213>;
749 interrupt-controller;
750 #interrupt-cells = <2>;
751 interrupt-parent = <&aic>;
760 i2c0_pins: i2c0-pins {
765 i2c1_pins: i2c1-pins {
770 i2c2_pins: i2c2-pins {
775 i2c3_pins: i2c3-pins {
780 i2c4_pins: i2c4-pins {
785 spi1_pins: spi1-pins {
792 spi3_pins: spi3-pins {
799 pcie_pins: pcie-pins {
808 compatible = "apple,t8112-pinctrl", "apple,pinctrl";
810 power-domains = <&ps_nub_gpio>;
812 gpio-controller;
813 #gpio-cells = <2>;
814 gpio-ranges = <&pinctrl_nub 0 0 24>;
817 interrupt-controller;
818 #interrupt-cells = <2>;
819 interrupt-parent = <&aic>;
829 pmgr_mini: power-management@23d280000 {
830 compatible = "apple,t8112-pmgr", "apple,pmgr", "syscon", "simple-mfd";
831 #address-cells = <1>;
832 #size-cells = <1>;
834 /* child nodes are added in t8103-pmgr.dtsi */
838 compatible = "apple,t8112-wdt", "apple,wdt";
841 interrupt-parent = <&aic>;
846 compatible = "apple,t8112-spmi", "apple,spmi";
848 #address-cells = <2>;
849 #size-cells = <0>;
852 compatible = "apple,stowe-pmic", "apple,spmi-nvmem";
855 nvmem-layout {
856 compatible = "fixed-layout";
857 #address-cells = <1>;
858 #size-cells = <1>;
860 fault_shadow: fault-shadow@867b {
868 boot_stage: boot-stage@f701 {
872 boot_error_count: boot-error-count@f702,0 {
877 panic_count: panic-count@f702,4 {
882 boot_error_stage: boot-error-stage@f703 {
886 shutdown_flag: shutdown-flag@f70f,3 {
891 pm_setting: pm-setting@f801 {
895 rtc_offset: rtc-offset@f900 {
903 compatible = "apple,t8112-pinctrl", "apple,pinctrl";
906 gpio-controller;
907 #gpio-cells = <2>;
908 gpio-ranges = <&pinctrl_smc 0 0 18>;
911 interrupt-controller;
912 #interrupt-cells = <2>;
913 interrupt-parent = <&aic>;
924 compatible = "apple,t8112-pinctrl", "apple,pinctrl";
927 gpio-controller;
928 #gpio-cells = <2>;
929 gpio-ranges = <&pinctrl_aop 0 0 54>;
932 interrupt-controller;
933 #interrupt-cells = <2>;
934 interrupt-parent = <&aic>;
945 compatible = "apple,t8112-asc-mailbox", "apple,asc-mailbox-v4";
947 interrupt-parent = <&aic>;
952 interrupt-names = "send-empty", "send-not-empty",
953 "recv-empty", "recv-not-empty";
954 #mbox-cells = <0>;
955 power-domains = <&ps_ans>;
959 compatible = "apple,t8112-sart", "apple,t6000-sart";
961 power-domains = <&ps_ans>;
964 nvme@27bcc0000 {
965 compatible = "apple,t8112-nvme-ans2", "apple,nvme-ans2";
968 reg-names = "nvme", "ans";
969 interrupt-parent = <&aic>;
973 power-domains = <&ps_ans>, <&ps_apcie_st>;
974 power-domain-names = "ans", "apcie0";
979 compatible = "apple,t8110-dart";
981 #iommu-cells = <1>;
982 interrupt-parent = <&aic>;
984 power-domains = <&ps_apcie_gp>;
988 compatible = "apple,t8110-dart";
990 #iommu-cells = <1>;
991 interrupt-parent = <&aic>;
993 power-domains = <&ps_apcie_gp>;
998 compatible = "apple,t8110-dart";
1000 #iommu-cells = <1>;
1001 interrupt-parent = <&aic>;
1003 power-domains = <&ps_apcie_gp>;
1008 compatible = "apple,t8110-dart";
1010 #iommu-cells = <1>;
1011 interrupt-parent = <&aic>;
1013 power-domains = <&ps_apcie_gp>;
1018 compatible = "apple,t8112-pcie", "apple,pcie";
1027 reg-names = "config", "rc", "port0", "port1", "port2", "port3";
1029 interrupt-parent = <&aic>;
1035 msi-controller;
1036 msi-parent = <&pcie0>;
1037 msi-ranges = <&aic AIC_IRQ 793 IRQ_TYPE_EDGE_RISING 32>;
1039 iommu-map = <0x100 &pcie0_dart 0 1>,
1043 iommu-map-mask = <0xff00>;
1045 bus-range = <0 4>;
1046 #address-cells = <3>;
1047 #size-cells = <2>;
1051 power-domains = <&ps_apcie_gp>;
1052 pinctrl-0 = <&pcie_pins>;
1053 pinctrl-names = "default";
1058 reset-gpios = <&pinctrl_ap 166 GPIO_ACTIVE_LOW>;
1060 #address-cells = <3>;
1061 #size-cells = <2>;
1064 interrupt-controller;
1065 #interrupt-cells = <1>;
1067 interrupt-map-mask = <0 0 0 7>;
1068 interrupt-map = <0 0 0 1 &port00 0 0 0 0>,
1077 reset-gpios = <&pinctrl_ap 167 GPIO_ACTIVE_LOW>;
1079 #address-cells = <3>;
1080 #size-cells = <2>;
1083 interrupt-controller;
1084 #interrupt-cells = <1>;
1086 interrupt-map-mask = <0 0 0 7>;
1087 interrupt-map = <0 0 0 1 &port01 0 0 0 0>,
1098 reset-gpios = <&pinctrl_ap 168 GPIO_ACTIVE_LOW>;
1100 #address-cells = <3>;
1101 #size-cells = <2>;
1104 interrupt-controller;
1105 #interrupt-cells = <1>;
1107 interrupt-map-mask = <0 0 0 7>;
1108 interrupt-map = <0 0 0 1 &port02 0 0 0 0>,
1120 //reset-gpios = <&pinctrl_ap 33 GPIO_ACTIVE_LOW>;
1122 #address-cells = <3>;
1123 #size-cells = <2>;
1126 interrupt-controller;
1127 #interrupt-cells = <1>;
1129 interrupt-map-mask = <0 0 0 7>;
1130 interrupt-map = <0 0 0 1 &port03 0 0 0 0>,
1141 #include "t8112-pmgr.dtsi"