Lines Matching +full:t8103 +full:- +full:cluster +full:- +full:cpufreq
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * Apple T8103 "M1" SoC
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
14 #include <dt-bindings/spmi/spmi.h>
17 compatible = "apple,t8103", "apple,arm-platform";
19 #address-cells = <2>;
20 #size-cells = <2>;
23 #address-cells = <2>;
24 #size-cells = <0>;
26 cpu-map {
62 enable-method = "spin-table";
63 cpu-release-addr = <0 0>; /* To be filled by loader */
64 operating-points-v2 = <&ecluster_opp>;
65 capacity-dmips-mhz = <714>;
66 performance-domains = <&cpufreq_e>;
67 next-level-cache = <&l2_cache_0>;
68 i-cache-size = <0x20000>;
69 d-cache-size = <0x10000>;
76 enable-method = "spin-table";
77 cpu-release-addr = <0 0>; /* To be filled by loader */
78 operating-points-v2 = <&ecluster_opp>;
79 capacity-dmips-mhz = <714>;
80 performance-domains = <&cpufreq_e>;
81 next-level-cache = <&l2_cache_0>;
82 i-cache-size = <0x20000>;
83 d-cache-size = <0x10000>;
90 enable-method = "spin-table";
91 cpu-release-addr = <0 0>; /* To be filled by loader */
92 operating-points-v2 = <&ecluster_opp>;
93 capacity-dmips-mhz = <714>;
94 performance-domains = <&cpufreq_e>;
95 next-level-cache = <&l2_cache_0>;
96 i-cache-size = <0x20000>;
97 d-cache-size = <0x10000>;
104 enable-method = "spin-table";
105 cpu-release-addr = <0 0>; /* To be filled by loader */
106 operating-points-v2 = <&ecluster_opp>;
107 capacity-dmips-mhz = <714>;
108 performance-domains = <&cpufreq_e>;
109 next-level-cache = <&l2_cache_0>;
110 i-cache-size = <0x20000>;
111 d-cache-size = <0x10000>;
118 enable-method = "spin-table";
119 cpu-release-addr = <0 0>; /* To be filled by loader */
120 operating-points-v2 = <&pcluster_opp>;
121 capacity-dmips-mhz = <1024>;
122 performance-domains = <&cpufreq_p>;
123 next-level-cache = <&l2_cache_1>;
124 i-cache-size = <0x30000>;
125 d-cache-size = <0x20000>;
132 enable-method = "spin-table";
133 cpu-release-addr = <0 0>; /* To be filled by loader */
134 operating-points-v2 = <&pcluster_opp>;
135 capacity-dmips-mhz = <1024>;
136 performance-domains = <&cpufreq_p>;
137 next-level-cache = <&l2_cache_1>;
138 i-cache-size = <0x30000>;
139 d-cache-size = <0x20000>;
146 enable-method = "spin-table";
147 cpu-release-addr = <0 0>; /* To be filled by loader */
148 operating-points-v2 = <&pcluster_opp>;
149 capacity-dmips-mhz = <1024>;
150 performance-domains = <&cpufreq_p>;
151 next-level-cache = <&l2_cache_1>;
152 i-cache-size = <0x30000>;
153 d-cache-size = <0x20000>;
160 enable-method = "spin-table";
161 cpu-release-addr = <0 0>; /* To be filled by loader */
162 operating-points-v2 = <&pcluster_opp>;
163 capacity-dmips-mhz = <1024>;
164 performance-domains = <&cpufreq_p>;
165 next-level-cache = <&l2_cache_1>;
166 i-cache-size = <0x30000>;
167 d-cache-size = <0x20000>;
170 l2_cache_0: l2-cache-0 {
172 cache-level = <2>;
173 cache-unified;
174 cache-size = <0x400000>;
177 l2_cache_1: l2-cache-1 {
179 cache-level = <2>;
180 cache-unified;
181 cache-size = <0xc00000>;
185 ecluster_opp: opp-table-0 {
186 compatible = "operating-points-v2";
189 opp-hz = /bits/ 64 <600000000>;
190 opp-level = <1>;
191 clock-latency-ns = <7500>;
194 opp-hz = /bits/ 64 <972000000>;
195 opp-level = <2>;
196 clock-latency-ns = <22000>;
199 opp-hz = /bits/ 64 <1332000000>;
200 opp-level = <3>;
201 clock-latency-ns = <27000>;
204 opp-hz = /bits/ 64 <1704000000>;
205 opp-level = <4>;
206 clock-latency-ns = <33000>;
209 opp-hz = /bits/ 64 <2064000000>;
210 opp-level = <5>;
211 clock-latency-ns = <50000>;
215 pcluster_opp: opp-table-1 {
216 compatible = "operating-points-v2";
219 opp-hz = /bits/ 64 <600000000>;
220 opp-level = <1>;
221 clock-latency-ns = <8000>;
224 opp-hz = /bits/ 64 <828000000>;
225 opp-level = <2>;
226 clock-latency-ns = <19000>;
229 opp-hz = /bits/ 64 <1056000000>;
230 opp-level = <3>;
231 clock-latency-ns = <21000>;
234 opp-hz = /bits/ 64 <1284000000>;
235 opp-level = <4>;
236 clock-latency-ns = <23000>;
239 opp-hz = /bits/ 64 <1500000000>;
240 opp-level = <5>;
241 clock-latency-ns = <24000>;
244 opp-hz = /bits/ 64 <1728000000>;
245 opp-level = <6>;
246 clock-latency-ns = <29000>;
249 opp-hz = /bits/ 64 <1956000000>;
250 opp-level = <7>;
251 clock-latency-ns = <31000>;
254 opp-hz = /bits/ 64 <2184000000>;
255 opp-level = <8>;
256 clock-latency-ns = <34000>;
259 opp-hz = /bits/ 64 <2388000000>;
260 opp-level = <9>;
261 clock-latency-ns = <36000>;
264 opp-hz = /bits/ 64 <2592000000>;
265 opp-level = <10>;
266 clock-latency-ns = <51000>;
269 opp-hz = /bits/ 64 <2772000000>;
270 opp-level = <11>;
271 clock-latency-ns = <54000>;
274 opp-hz = /bits/ 64 <2988000000>;
275 opp-level = <12>;
276 clock-latency-ns = <55000>;
281 opp-hz = /bits/ 64 <3096000000>;
282 opp-level = <13>;
283 clock-latency-ns = <55000>;
284 turbo-mode;
287 opp-hz = /bits/ 64 <3144000000>;
288 opp-level = <14>;
289 clock-latency-ns = <56000>;
290 turbo-mode;
293 opp-hz = /bits/ 64 <3204000000>;
294 opp-level = <15>;
295 clock-latency-ns = <56000>;
296 turbo-mode;
302 compatible = "arm,armv8-timer";
303 interrupt-parent = <&aic>;
304 interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt";
311 pmu-e {
312 compatible = "apple,icestorm-pmu";
313 interrupt-parent = <&aic>;
317 pmu-p {
318 compatible = "apple,firestorm-pmu";
319 interrupt-parent = <&aic>;
323 clkref: clock-ref {
324 compatible = "fixed-clock";
325 #clock-cells = <0>;
326 clock-frequency = <24000000>;
327 clock-output-names = "clkref";
330 clk_120m: clock-120m {
331 compatible = "fixed-clock";
332 #clock-cells = <0>;
333 clock-frequency = <120000000>;
334 clock-output-names = "clk_120m";
337 clk_200m: clock-200m {
338 compatible = "fixed-clock";
339 #clock-cells = <0>;
340 clock-frequency = <200000000>;
341 clock-output-names = "clk_200m";
348 nco_clkref: clock-ref-nco {
349 compatible = "fixed-clock";
350 #clock-cells = <0>;
351 clock-output-names = "nco_ref";
355 compatible = "simple-bus";
356 #address-cells = <2>;
357 #size-cells = <2>;
360 nonposted-mmio;
362 cpufreq_e: performance-controller@210e20000 {
363 compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
365 #performance-domain-cells = <0>;
368 cpufreq_p: performance-controller@211e20000 {
369 compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
371 #performance-domain-cells = <0>;
374 display_dfr: display-pipe@228200000 {
375 compatible = "apple,t8103-display-pipe", "apple,h7-display-pipe";
378 reg-names = "be", "fe";
379 power-domains = <&ps_dispdfr_fe>, <&ps_dispdfr_be>;
380 interrupt-parent = <&aic>;
383 interrupt-names = "be", "fe";
389 remote-endpoint = <&dfr_mipi_in_adp>;
395 compatible = "apple,t8103-dart";
397 interrupt-parent = <&aic>;
399 #iommu-cells = <1>;
400 power-domains = <&ps_dispdfr_fe>;
405 compatible = "apple,t8103-display-pipe-mipi", "apple,h7-display-pipe-mipi";
407 power-domains = <&ps_mipi_dsi>;
408 #address-cells = <1>;
409 #size-cells = <0>;
413 #address-cells = <1>;
414 #size-cells = <0>;
418 #address-cells = <1>;
419 #size-cells = <0>;
423 remote-endpoint = <&dfr_adp_out_mipi>;
429 #address-cells = <1>;
430 #size-cells = <0>;
436 compatible = "apple,t8103-dart";
438 interrupt-parent = <&aic>;
440 #iommu-cells = <1>;
441 power-domains = <&ps_sio_cpu>;
445 compatible = "apple,t8103-i2c", "apple,i2c";
448 interrupt-parent = <&aic>;
450 pinctrl-0 = <&i2c0_pins>;
451 pinctrl-names = "default";
452 #address-cells = <0x1>;
453 #size-cells = <0x0>;
454 power-domains = <&ps_i2c0>;
458 compatible = "apple,t8103-i2c", "apple,i2c";
461 interrupt-parent = <&aic>;
463 pinctrl-0 = <&i2c1_pins>;
464 pinctrl-names = "default";
465 #address-cells = <0x1>;
466 #size-cells = <0x0>;
467 power-domains = <&ps_i2c1>;
471 compatible = "apple,t8103-i2c", "apple,i2c";
474 interrupt-parent = <&aic>;
476 pinctrl-0 = <&i2c2_pins>;
477 pinctrl-names = "default";
478 #address-cells = <0x1>;
479 #size-cells = <0x0>;
481 power-domains = <&ps_i2c2>;
485 compatible = "apple,t8103-i2c", "apple,i2c";
488 interrupt-parent = <&aic>;
490 pinctrl-0 = <&i2c3_pins>;
491 pinctrl-names = "default";
492 #address-cells = <0x1>;
493 #size-cells = <0x0>;
494 power-domains = <&ps_i2c3>;
498 compatible = "apple,t8103-i2c", "apple,i2c";
501 interrupt-parent = <&aic>;
503 pinctrl-0 = <&i2c4_pins>;
504 pinctrl-names = "default";
505 #address-cells = <0x1>;
506 #size-cells = <0x0>;
507 power-domains = <&ps_i2c4>;
512 compatible = "apple,t8103-fpwm", "apple,s5l-fpwm";
514 power-domains = <&ps_fpwm1>;
516 #pwm-cells = <2>;
521 compatible = "apple,t8103-spi", "apple,spi";
523 interrupt-parent = <&aic>;
526 pinctrl-0 = <&spi0_pins>;
527 pinctrl-names = "default";
528 power-domains = <&ps_spi0>;
529 #address-cells = <1>;
530 #size-cells = <0>;
535 compatible = "apple,t8103-spi", "apple,spi";
537 interrupt-parent = <&aic>;
540 pinctrl-0 = <&spi1_pins>;
541 pinctrl-names = "default";
542 power-domains = <&ps_spi1>;
543 #address-cells = <1>;
544 #size-cells = <0>;
549 compatible = "apple,t8103-spi", "apple,spi";
551 interrupt-parent = <&aic>;
554 pinctrl-0 = <&spi3_pins>;
555 pinctrl-names = "default";
556 power-domains = <&ps_spi3>;
557 #address-cells = <1>;
558 #size-cells = <0>;
563 compatible = "apple,s5l-uart";
565 reg-io-width = <4>;
566 interrupt-parent = <&aic>;
573 clock-names = "uart", "clk_uart_baud0";
574 power-domains = <&ps_uart0>;
579 compatible = "apple,s5l-uart";
581 reg-io-width = <4>;
582 interrupt-parent = <&aic>;
585 clock-names = "uart", "clk_uart_baud0";
586 power-domains = <&ps_uart2>;
590 admac: dma-controller@238200000 {
591 compatible = "apple,t8103-admac", "apple,admac";
593 dma-channels = <24>;
594 interrupts-extended = <0>,
598 #dma-cells = <1>;
600 power-domains = <&ps_sio_adma>;
605 compatible = "apple,t8103-mca", "apple,mca";
609 interrupt-parent = <&aic>;
620 power-domains = <&ps_audio_p>, <&ps_mca0>, <&ps_mca1>,
628 dma-names = "tx0a", "rx0a", "tx0b", "rx0b",
635 #sound-dai-cells = <1>;
638 nco: clock-controller@23b044000 {
639 compatible = "apple,t8103-nco", "apple,nco";
642 #clock-cells = <1>;
645 aic: interrupt-controller@23b100000 {
646 compatible = "apple,t8103-aic", "apple,aic";
647 #interrupt-cells = <3>;
648 interrupt-controller;
650 power-domains = <&ps_aic>;
653 e-core-pmu-affinity {
654 apple,fiq-index = <AIC_CPU_PMU_E>;
658 p-core-pmu-affinity {
659 apple,fiq-index = <AIC_CPU_PMU_P>;
665 pmgr: power-management@23b700000 {
666 compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd";
667 #address-cells = <1>;
668 #size-cells = <1>;
673 compatible = "apple,t8103-pinctrl", "apple,pinctrl";
675 power-domains = <&ps_gpio>;
677 gpio-controller;
678 #gpio-cells = <2>;
679 gpio-ranges = <&pinctrl_ap 0 0 212>;
682 interrupt-controller;
683 #interrupt-cells = <2>;
684 interrupt-parent = <&aic>;
693 i2c0_pins: i2c0-pins {
698 i2c1_pins: i2c1-pins {
703 i2c2_pins: i2c2-pins {
708 i2c3_pins: i2c3-pins {
713 i2c4_pins: i2c4-pins {
718 spi0_pins: spi0-pins {
724 spi1_pins: spi1-pins {
731 spi3_pins: spi3-pins {
738 pcie_pins: pcie-pins {
746 compatible = "apple,t8103-spmi", "apple,spmi";
748 #address-cells = <2>;
749 #size-cells = <0>;
752 compatible = "apple,sera-pmic", "apple,spmi-nvmem";
755 nvmem-layout {
756 compatible = "fixed-layout";
757 #address-cells = <1>;
758 #size-cells = <1>;
760 boot_stage: boot-stage@9f01 {
764 boot_error_count: boot-error-count@9f02 {
769 panic_count: panic-count@9f02 {
774 boot_error_stage: boot-error-stage@9f03 {
778 shutdown_flag: shutdown-flag@9f0f {
783 fault_shadow: fault-shadow@a67b {
791 pm_setting: pm-setting@d001 {
795 rtc_offset: rtc-offset@d100 {
803 compatible = "apple,t8103-pinctrl", "apple,pinctrl";
805 power-domains = <&ps_nub_gpio>;
807 gpio-controller;
808 #gpio-cells = <2>;
809 gpio-ranges = <&pinctrl_nub 0 0 23>;
812 interrupt-controller;
813 #interrupt-cells = <2>;
814 interrupt-parent = <&aic>;
824 pmgr_mini: power-management@23d280000 {
825 compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd";
826 #address-cells = <1>;
827 #size-cells = <1>;
832 compatible = "apple,t8103-wdt", "apple,wdt";
835 interrupt-parent = <&aic>;
840 compatible = "apple,t8103-pinctrl", "apple,pinctrl";
843 gpio-controller;
844 #gpio-cells = <2>;
845 gpio-ranges = <&pinctrl_smc 0 0 16>;
848 interrupt-controller;
849 #interrupt-cells = <2>;
850 interrupt-parent = <&aic>;
861 compatible = "apple,t8103-pinctrl", "apple,pinctrl";
864 gpio-controller;
865 #gpio-cells = <2>;
866 gpio-ranges = <&pinctrl_aop 0 0 42>;
869 interrupt-controller;
870 #interrupt-cells = <2>;
871 interrupt-parent = <&aic>;
882 compatible = "apple,t8103-asc-mailbox", "apple,asc-mailbox-v4";
884 interrupt-parent = <&aic>;
889 interrupt-names = "send-empty", "send-not-empty",
890 "recv-empty", "recv-not-empty";
891 #mbox-cells = <0>;
892 power-domains = <&ps_ans2>;
896 compatible = "apple,t8103-sart";
898 power-domains = <&ps_ans2>;
902 compatible = "apple,t8103-nvme-ans2", "apple,nvme-ans2";
905 reg-names = "nvme", "ans";
906 interrupt-parent = <&aic>;
910 power-domains = <&ps_ans2>, <&ps_apcie_st>;
911 power-domain-names = "ans", "apcie0";
916 compatible = "apple,t8103-dart";
918 #iommu-cells = <1>;
919 interrupt-parent = <&aic>;
921 power-domains = <&ps_apcie_gp>;
925 compatible = "apple,t8103-dart";
927 #iommu-cells = <1>;
928 interrupt-parent = <&aic>;
930 power-domains = <&ps_apcie_gp>;
935 compatible = "apple,t8103-dart";
937 #iommu-cells = <1>;
938 interrupt-parent = <&aic>;
940 power-domains = <&ps_apcie_gp>;
945 compatible = "apple,t8103-pcie", "apple,pcie";
953 reg-names = "config", "rc", "port0", "port1", "port2";
955 interrupt-parent = <&aic>;
960 msi-controller;
961 msi-parent = <&pcie0>;
962 msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>;
965 iommu-map = <0x100 &pcie0_dart_0 1 1>,
968 iommu-map-mask = <0xff00>;
970 bus-range = <0 3>;
971 #address-cells = <3>;
972 #size-cells = <2>;
976 power-domains = <&ps_apcie_gp>;
977 pinctrl-0 = <&pcie_pins>;
978 pinctrl-names = "default";
983 reset-gpios = <&pinctrl_ap 152 GPIO_ACTIVE_LOW>;
985 #address-cells = <3>;
986 #size-cells = <2>;
989 interrupt-controller;
990 #interrupt-cells = <1>;
992 interrupt-map-mask = <0 0 0 7>;
993 interrupt-map = <0 0 0 1 &port00 0 0 0 0>,
1002 reset-gpios = <&pinctrl_ap 153 GPIO_ACTIVE_LOW>;
1004 #address-cells = <3>;
1005 #size-cells = <2>;
1008 interrupt-controller;
1009 #interrupt-cells = <1>;
1011 interrupt-map-mask = <0 0 0 7>;
1012 interrupt-map = <0 0 0 1 &port01 0 0 0 0>,
1022 reset-gpios = <&pinctrl_ap 33 GPIO_ACTIVE_LOW>;
1024 #address-cells = <3>;
1025 #size-cells = <2>;
1028 interrupt-controller;
1029 #interrupt-cells = <1>;
1031 interrupt-map-mask = <0 0 0 7>;
1032 interrupt-map = <0 0 0 1 &port02 0 0 0 0>,
1042 #include "t8103-pmgr.dtsi"