Lines Matching +full:s5l +full:- +full:fpwm
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
16 compatible = "apple,t8103", "apple,arm-platform";
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <2>;
23 #size-cells = <0>;
25 cpu-map {
61 enable-method = "spin-table";
62 cpu-release-addr = <0 0>; /* To be filled by loader */
63 operating-points-v2 = <&ecluster_opp>;
64 capacity-dmips-mhz = <714>;
65 performance-domains = <&cpufreq_e>;
66 next-level-cache = <&l2_cache_0>;
67 i-cache-size = <0x20000>;
68 d-cache-size = <0x10000>;
75 enable-method = "spin-table";
76 cpu-release-addr = <0 0>; /* To be filled by loader */
77 operating-points-v2 = <&ecluster_opp>;
78 capacity-dmips-mhz = <714>;
79 performance-domains = <&cpufreq_e>;
80 next-level-cache = <&l2_cache_0>;
81 i-cache-size = <0x20000>;
82 d-cache-size = <0x10000>;
89 enable-method = "spin-table";
90 cpu-release-addr = <0 0>; /* To be filled by loader */
91 operating-points-v2 = <&ecluster_opp>;
92 capacity-dmips-mhz = <714>;
93 performance-domains = <&cpufreq_e>;
94 next-level-cache = <&l2_cache_0>;
95 i-cache-size = <0x20000>;
96 d-cache-size = <0x10000>;
103 enable-method = "spin-table";
104 cpu-release-addr = <0 0>; /* To be filled by loader */
105 operating-points-v2 = <&ecluster_opp>;
106 capacity-dmips-mhz = <714>;
107 performance-domains = <&cpufreq_e>;
108 next-level-cache = <&l2_cache_0>;
109 i-cache-size = <0x20000>;
110 d-cache-size = <0x10000>;
117 enable-method = "spin-table";
118 cpu-release-addr = <0 0>; /* To be filled by loader */
119 operating-points-v2 = <&pcluster_opp>;
120 capacity-dmips-mhz = <1024>;
121 performance-domains = <&cpufreq_p>;
122 next-level-cache = <&l2_cache_1>;
123 i-cache-size = <0x30000>;
124 d-cache-size = <0x20000>;
131 enable-method = "spin-table";
132 cpu-release-addr = <0 0>; /* To be filled by loader */
133 operating-points-v2 = <&pcluster_opp>;
134 capacity-dmips-mhz = <1024>;
135 performance-domains = <&cpufreq_p>;
136 next-level-cache = <&l2_cache_1>;
137 i-cache-size = <0x30000>;
138 d-cache-size = <0x20000>;
145 enable-method = "spin-table";
146 cpu-release-addr = <0 0>; /* To be filled by loader */
147 operating-points-v2 = <&pcluster_opp>;
148 capacity-dmips-mhz = <1024>;
149 performance-domains = <&cpufreq_p>;
150 next-level-cache = <&l2_cache_1>;
151 i-cache-size = <0x30000>;
152 d-cache-size = <0x20000>;
159 enable-method = "spin-table";
160 cpu-release-addr = <0 0>; /* To be filled by loader */
161 operating-points-v2 = <&pcluster_opp>;
162 capacity-dmips-mhz = <1024>;
163 performance-domains = <&cpufreq_p>;
164 next-level-cache = <&l2_cache_1>;
165 i-cache-size = <0x30000>;
166 d-cache-size = <0x20000>;
169 l2_cache_0: l2-cache-0 {
171 cache-level = <2>;
172 cache-unified;
173 cache-size = <0x400000>;
176 l2_cache_1: l2-cache-1 {
178 cache-level = <2>;
179 cache-unified;
180 cache-size = <0xc00000>;
184 ecluster_opp: opp-table-0 {
185 compatible = "operating-points-v2";
188 opp-hz = /bits/ 64 <600000000>;
189 opp-level = <1>;
190 clock-latency-ns = <7500>;
193 opp-hz = /bits/ 64 <972000000>;
194 opp-level = <2>;
195 clock-latency-ns = <22000>;
198 opp-hz = /bits/ 64 <1332000000>;
199 opp-level = <3>;
200 clock-latency-ns = <27000>;
203 opp-hz = /bits/ 64 <1704000000>;
204 opp-level = <4>;
205 clock-latency-ns = <33000>;
208 opp-hz = /bits/ 64 <2064000000>;
209 opp-level = <5>;
210 clock-latency-ns = <50000>;
214 pcluster_opp: opp-table-1 {
215 compatible = "operating-points-v2";
218 opp-hz = /bits/ 64 <600000000>;
219 opp-level = <1>;
220 clock-latency-ns = <8000>;
223 opp-hz = /bits/ 64 <828000000>;
224 opp-level = <2>;
225 clock-latency-ns = <19000>;
228 opp-hz = /bits/ 64 <1056000000>;
229 opp-level = <3>;
230 clock-latency-ns = <21000>;
233 opp-hz = /bits/ 64 <1284000000>;
234 opp-level = <4>;
235 clock-latency-ns = <23000>;
238 opp-hz = /bits/ 64 <1500000000>;
239 opp-level = <5>;
240 clock-latency-ns = <24000>;
243 opp-hz = /bits/ 64 <1728000000>;
244 opp-level = <6>;
245 clock-latency-ns = <29000>;
248 opp-hz = /bits/ 64 <1956000000>;
249 opp-level = <7>;
250 clock-latency-ns = <31000>;
253 opp-hz = /bits/ 64 <2184000000>;
254 opp-level = <8>;
255 clock-latency-ns = <34000>;
258 opp-hz = /bits/ 64 <2388000000>;
259 opp-level = <9>;
260 clock-latency-ns = <36000>;
263 opp-hz = /bits/ 64 <2592000000>;
264 opp-level = <10>;
265 clock-latency-ns = <51000>;
268 opp-hz = /bits/ 64 <2772000000>;
269 opp-level = <11>;
270 clock-latency-ns = <54000>;
273 opp-hz = /bits/ 64 <2988000000>;
274 opp-level = <12>;
275 clock-latency-ns = <55000>;
280 opp-hz = /bits/ 64 <3096000000>;
281 opp-level = <13>;
282 clock-latency-ns = <55000>;
283 turbo-mode;
286 opp-hz = /bits/ 64 <3144000000>;
287 opp-level = <14>;
288 clock-latency-ns = <56000>;
289 turbo-mode;
292 opp-hz = /bits/ 64 <3204000000>;
293 opp-level = <15>;
294 clock-latency-ns = <56000>;
295 turbo-mode;
301 compatible = "arm,armv8-timer";
302 interrupt-parent = <&aic>;
303 interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt";
310 pmu-e {
311 compatible = "apple,icestorm-pmu";
312 interrupt-parent = <&aic>;
316 pmu-p {
317 compatible = "apple,firestorm-pmu";
318 interrupt-parent = <&aic>;
322 clkref: clock-ref {
323 compatible = "fixed-clock";
324 #clock-cells = <0>;
325 clock-frequency = <24000000>;
326 clock-output-names = "clkref";
329 clk_120m: clock-120m {
330 compatible = "fixed-clock";
331 #clock-cells = <0>;
332 clock-frequency = <120000000>;
333 clock-output-names = "clk_120m";
336 clk_200m: clock-200m {
337 compatible = "fixed-clock";
338 #clock-cells = <0>;
339 clock-frequency = <200000000>;
340 clock-output-names = "clk_200m";
347 nco_clkref: clock-ref-nco {
348 compatible = "fixed-clock";
349 #clock-cells = <0>;
350 clock-output-names = "nco_ref";
354 compatible = "simple-bus";
355 #address-cells = <2>;
356 #size-cells = <2>;
359 nonposted-mmio;
361 cpufreq_e: performance-controller@210e20000 {
362 compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
364 #performance-domain-cells = <0>;
367 cpufreq_p: performance-controller@211e20000 {
368 compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
370 #performance-domain-cells = <0>;
373 display_dfr: display-pipe@228200000 {
374 compatible = "apple,t8103-display-pipe", "apple,h7-display-pipe";
377 reg-names = "be", "fe";
378 power-domains = <&ps_dispdfr_fe>, <&ps_dispdfr_be>;
379 interrupt-parent = <&aic>;
382 interrupt-names = "be", "fe";
388 remote-endpoint = <&dfr_mipi_in_adp>;
394 compatible = "apple,t8103-dart";
396 interrupt-parent = <&aic>;
398 #iommu-cells = <1>;
399 power-domains = <&ps_dispdfr_fe>;
404 compatible = "apple,t8103-display-pipe-mipi", "apple,h7-display-pipe-mipi";
406 power-domains = <&ps_mipi_dsi>;
407 #address-cells = <1>;
408 #size-cells = <0>;
412 #address-cells = <1>;
413 #size-cells = <0>;
417 #address-cells = <1>;
418 #size-cells = <0>;
422 remote-endpoint = <&dfr_adp_out_mipi>;
428 #address-cells = <1>;
429 #size-cells = <0>;
435 compatible = "apple,t8103-dart";
437 interrupt-parent = <&aic>;
439 #iommu-cells = <1>;
440 power-domains = <&ps_sio_cpu>;
444 compatible = "apple,t8103-i2c", "apple,i2c";
447 interrupt-parent = <&aic>;
449 pinctrl-0 = <&i2c0_pins>;
450 pinctrl-names = "default";
451 #address-cells = <0x1>;
452 #size-cells = <0x0>;
453 power-domains = <&ps_i2c0>;
457 compatible = "apple,t8103-i2c", "apple,i2c";
460 interrupt-parent = <&aic>;
462 pinctrl-0 = <&i2c1_pins>;
463 pinctrl-names = "default";
464 #address-cells = <0x1>;
465 #size-cells = <0x0>;
466 power-domains = <&ps_i2c1>;
470 compatible = "apple,t8103-i2c", "apple,i2c";
473 interrupt-parent = <&aic>;
475 pinctrl-0 = <&i2c2_pins>;
476 pinctrl-names = "default";
477 #address-cells = <0x1>;
478 #size-cells = <0x0>;
480 power-domains = <&ps_i2c2>;
484 compatible = "apple,t8103-i2c", "apple,i2c";
487 interrupt-parent = <&aic>;
489 pinctrl-0 = <&i2c3_pins>;
490 pinctrl-names = "default";
491 #address-cells = <0x1>;
492 #size-cells = <0x0>;
493 power-domains = <&ps_i2c3>;
497 compatible = "apple,t8103-i2c", "apple,i2c";
500 interrupt-parent = <&aic>;
502 pinctrl-0 = <&i2c4_pins>;
503 pinctrl-names = "default";
504 #address-cells = <0x1>;
505 #size-cells = <0x0>;
506 power-domains = <&ps_i2c4>;
511 compatible = "apple,t8103-fpwm", "apple,s5l-fpwm";
513 power-domains = <&ps_fpwm1>;
515 #pwm-cells = <2>;
520 compatible = "apple,t8103-spi", "apple,spi";
522 interrupt-parent = <&aic>;
525 pinctrl-0 = <&spi0_pins>;
526 pinctrl-names = "default";
527 power-domains = <&ps_spi0>;
528 #address-cells = <1>;
529 #size-cells = <0>;
534 compatible = "apple,t8103-spi", "apple,spi";
536 interrupt-parent = <&aic>;
539 pinctrl-0 = <&spi1_pins>;
540 pinctrl-names = "default";
541 power-domains = <&ps_spi1>;
542 #address-cells = <1>;
543 #size-cells = <0>;
548 compatible = "apple,t8103-spi", "apple,spi";
550 interrupt-parent = <&aic>;
553 pinctrl-0 = <&spi3_pins>;
554 pinctrl-names = "default";
555 power-domains = <&ps_spi3>;
556 #address-cells = <1>;
557 #size-cells = <0>;
562 compatible = "apple,s5l-uart";
564 reg-io-width = <4>;
565 interrupt-parent = <&aic>;
572 clock-names = "uart", "clk_uart_baud0";
573 power-domains = <&ps_uart0>;
578 compatible = "apple,s5l-uart";
580 reg-io-width = <4>;
581 interrupt-parent = <&aic>;
584 clock-names = "uart", "clk_uart_baud0";
585 power-domains = <&ps_uart2>;
589 admac: dma-controller@238200000 {
590 compatible = "apple,t8103-admac", "apple,admac";
592 dma-channels = <24>;
593 interrupts-extended = <0>,
597 #dma-cells = <1>;
599 power-domains = <&ps_sio_adma>;
604 compatible = "apple,t8103-mca", "apple,mca";
608 interrupt-parent = <&aic>;
619 power-domains = <&ps_audio_p>, <&ps_mca0>, <&ps_mca1>,
627 dma-names = "tx0a", "rx0a", "tx0b", "rx0b",
634 #sound-dai-cells = <1>;
637 nco: clock-controller@23b044000 {
638 compatible = "apple,t8103-nco", "apple,nco";
641 #clock-cells = <1>;
644 aic: interrupt-controller@23b100000 {
645 compatible = "apple,t8103-aic", "apple,aic";
646 #interrupt-cells = <3>;
647 interrupt-controller;
649 power-domains = <&ps_aic>;
652 e-core-pmu-affinity {
653 apple,fiq-index = <AIC_CPU_PMU_E>;
657 p-core-pmu-affinity {
658 apple,fiq-index = <AIC_CPU_PMU_P>;
664 pmgr: power-management@23b700000 {
665 compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd";
666 #address-cells = <1>;
667 #size-cells = <1>;
672 compatible = "apple,t8103-pinctrl", "apple,pinctrl";
674 power-domains = <&ps_gpio>;
676 gpio-controller;
677 #gpio-cells = <2>;
678 gpio-ranges = <&pinctrl_ap 0 0 212>;
681 interrupt-controller;
682 #interrupt-cells = <2>;
683 interrupt-parent = <&aic>;
692 i2c0_pins: i2c0-pins {
697 i2c1_pins: i2c1-pins {
702 i2c2_pins: i2c2-pins {
707 i2c3_pins: i2c3-pins {
712 i2c4_pins: i2c4-pins {
717 spi0_pins: spi0-pins {
723 spi1_pins: spi1-pins {
730 spi3_pins: spi3-pins {
737 pcie_pins: pcie-pins {
745 compatible = "apple,t8103-pinctrl", "apple,pinctrl";
747 power-domains = <&ps_nub_gpio>;
749 gpio-controller;
750 #gpio-cells = <2>;
751 gpio-ranges = <&pinctrl_nub 0 0 23>;
754 interrupt-controller;
755 #interrupt-cells = <2>;
756 interrupt-parent = <&aic>;
766 pmgr_mini: power-management@23d280000 {
767 compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd";
768 #address-cells = <1>;
769 #size-cells = <1>;
774 compatible = "apple,t8103-wdt", "apple,wdt";
777 interrupt-parent = <&aic>;
782 compatible = "apple,t8103-pinctrl", "apple,pinctrl";
785 gpio-controller;
786 #gpio-cells = <2>;
787 gpio-ranges = <&pinctrl_smc 0 0 16>;
790 interrupt-controller;
791 #interrupt-cells = <2>;
792 interrupt-parent = <&aic>;
803 compatible = "apple,t8103-pinctrl", "apple,pinctrl";
806 gpio-controller;
807 #gpio-cells = <2>;
808 gpio-ranges = <&pinctrl_aop 0 0 42>;
811 interrupt-controller;
812 #interrupt-cells = <2>;
813 interrupt-parent = <&aic>;
824 compatible = "apple,t8103-asc-mailbox", "apple,asc-mailbox-v4";
826 interrupt-parent = <&aic>;
831 interrupt-names = "send-empty", "send-not-empty",
832 "recv-empty", "recv-not-empty";
833 #mbox-cells = <0>;
834 power-domains = <&ps_ans2>;
838 compatible = "apple,t8103-sart";
840 power-domains = <&ps_ans2>;
844 compatible = "apple,t8103-nvme-ans2", "apple,nvme-ans2";
847 reg-names = "nvme", "ans";
848 interrupt-parent = <&aic>;
852 power-domains = <&ps_ans2>, <&ps_apcie_st>;
853 power-domain-names = "ans", "apcie0";
858 compatible = "apple,t8103-dart";
860 #iommu-cells = <1>;
861 interrupt-parent = <&aic>;
863 power-domains = <&ps_apcie_gp>;
867 compatible = "apple,t8103-dart";
869 #iommu-cells = <1>;
870 interrupt-parent = <&aic>;
872 power-domains = <&ps_apcie_gp>;
877 compatible = "apple,t8103-dart";
879 #iommu-cells = <1>;
880 interrupt-parent = <&aic>;
882 power-domains = <&ps_apcie_gp>;
887 compatible = "apple,t8103-pcie", "apple,pcie";
895 reg-names = "config", "rc", "port0", "port1", "port2";
897 interrupt-parent = <&aic>;
902 msi-controller;
903 msi-parent = <&pcie0>;
904 msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>;
907 iommu-map = <0x100 &pcie0_dart_0 1 1>,
910 iommu-map-mask = <0xff00>;
912 bus-range = <0 3>;
913 #address-cells = <3>;
914 #size-cells = <2>;
918 power-domains = <&ps_apcie_gp>;
919 pinctrl-0 = <&pcie_pins>;
920 pinctrl-names = "default";
925 reset-gpios = <&pinctrl_ap 152 GPIO_ACTIVE_LOW>;
927 #address-cells = <3>;
928 #size-cells = <2>;
931 interrupt-controller;
932 #interrupt-cells = <1>;
934 interrupt-map-mask = <0 0 0 7>;
935 interrupt-map = <0 0 0 1 &port00 0 0 0 0>,
944 reset-gpios = <&pinctrl_ap 153 GPIO_ACTIVE_LOW>;
946 #address-cells = <3>;
947 #size-cells = <2>;
950 interrupt-controller;
951 #interrupt-cells = <1>;
953 interrupt-map-mask = <0 0 0 7>;
954 interrupt-map = <0 0 0 1 &port01 0 0 0 0>,
964 reset-gpios = <&pinctrl_ap 33 GPIO_ACTIVE_LOW>;
966 #address-cells = <3>;
967 #size-cells = <2>;
970 interrupt-controller;
971 #interrupt-cells = <1>;
973 interrupt-map-mask = <0 0 0 7>;
974 interrupt-map = <0 0 0 1 &port02 0 0 0 0>,
984 #include "t8103-pmgr.dtsi"