Lines Matching +full:0 +full:x3b100000
28 #size-cells = <0>;
62 cpu_e0: cpu@0 {
65 reg = <0x0 0x0>;
67 cpu-release-addr = <0 0>; /* To be filled by loader */
72 i-cache-size = <0x20000>;
73 d-cache-size = <0x10000>;
79 reg = <0x0 0x1>;
81 cpu-release-addr = <0 0>; /* To be filled by loader */
86 i-cache-size = <0x20000>;
87 d-cache-size = <0x10000>;
93 reg = <0x0 0x2>;
95 cpu-release-addr = <0 0>; /* To be filled by loader */
100 i-cache-size = <0x20000>;
101 d-cache-size = <0x10000>;
107 reg = <0x0 0x3>;
109 cpu-release-addr = <0 0>; /* To be filled by loader */
114 i-cache-size = <0x20000>;
115 d-cache-size = <0x10000>;
121 reg = <0x0 0x10100>;
123 cpu-release-addr = <0 0>; /* To be filled by loader */
128 i-cache-size = <0x30000>;
129 d-cache-size = <0x20000>;
135 reg = <0x0 0x10101>;
137 cpu-release-addr = <0 0>; /* To be filled by loader */
142 i-cache-size = <0x30000>;
143 d-cache-size = <0x20000>;
149 reg = <0x0 0x10102>;
151 cpu-release-addr = <0 0>; /* To be filled by loader */
156 i-cache-size = <0x30000>;
157 d-cache-size = <0x20000>;
163 reg = <0x0 0x10103>;
165 cpu-release-addr = <0 0>; /* To be filled by loader */
170 i-cache-size = <0x30000>;
171 d-cache-size = <0x20000>;
174 l2_cache_0: l2-cache-0 {
178 cache-size = <0x400000>;
185 cache-size = <0xc00000>;
189 ecluster_opp: opp-table-0 {
282 #if 0
329 #clock-cells = <0>;
336 #clock-cells = <0>;
343 #clock-cells = <0>;
354 #clock-cells = <0>;
398 reg = <0x2 0x6400000 0 0x40000>,
399 <0x2 0x4000000 0 0x1000000>;
408 apple,firmware-abi = <0 0 0>;
413 reg = <0x2 0x6408000 0x0 0x4000>;
421 #mbox-cells = <0>;
426 reg = <0x2 0x10e20000 0 0x1000>;
427 #performance-domain-cells = <0>;
432 reg = <0x2 0x11e20000 0 0x1000>;
433 #performance-domain-cells = <0>;
438 reg = <0x2 0x28200000 0x0 0xc000>,
439 <0x2 0x28400000 0x0 0x4000>;
446 iommus = <&displaydfr_dart 0>;
458 reg = <0x2 0x28304000 0x0 0x4000>;
468 reg = <0x2 0x28600000 0x0 0x100000>;
474 #size-cells = <0>;
476 dfr_mipi_in: port@0 {
477 reg = <0>;
479 #size-cells = <0>;
481 dfr_mipi_in_adp: endpoint@0 {
482 reg = <0>;
490 #size-cells = <0>;
497 reg = <0x2 0x35004000 0x0 0x4000>;
506 reg = <0x2 0x35010000 0x0 0x4000>;
510 pinctrl-0 = <&i2c0_pins>;
512 #address-cells = <0x1>;
513 #size-cells = <0x0>;
519 reg = <0x2 0x35014000 0x0 0x4000>;
523 pinctrl-0 = <&i2c1_pins>;
525 #address-cells = <0x1>;
526 #size-cells = <0x0>;
532 reg = <0x2 0x35018000 0x0 0x4000>;
536 pinctrl-0 = <&i2c2_pins>;
538 #address-cells = <0x1>;
539 #size-cells = <0x0>;
546 reg = <0x2 0x3501c000 0x0 0x4000>;
550 pinctrl-0 = <&i2c3_pins>;
552 #address-cells = <0x1>;
553 #size-cells = <0x0>;
559 reg = <0x2 0x35020000 0x0 0x4000>;
563 pinctrl-0 = <&i2c4_pins>;
565 #address-cells = <0x1>;
566 #size-cells = <0x0>;
573 reg = <0x2 0x35044000 0x0 0x4000>;
582 reg = <0x2 0x35100000 0x0 0x4000>;
586 pinctrl-0 = <&spi0_pins>;
590 #size-cells = <0>;
596 reg = <0x2 0x35104000 0x0 0x4000>;
600 pinctrl-0 = <&spi1_pins>;
604 #size-cells = <0>;
610 reg = <0x2 0x3510c000 0x0 0x4000>;
614 pinctrl-0 = <&spi3_pins>;
618 #size-cells = <0>;
624 reg = <0x2 0x35200000 0x0 0x1000>;
640 reg = <0x2 0x35208000 0x0 0x1000>;
652 reg = <0x2 0x38200000 0x0 0x34000>;
654 interrupts-extended = <0>,
656 <0>,
657 <0>;
666 reg = <0x2 0x38400000 0x0 0x18000>,
667 <0x2 0x38300000 0x0 0x30000>;
678 clocks = <&nco 0>, <&nco 1>, <&nco 2>,
682 dmas = <&admac 0>, <&admac 1>, <&admac 2>, <&admac 3>,
700 reg = <0x2 0x3b044000 0x0 0x14000>;
709 reg = <0x2 0x3b100000 0x0 0x8000>;
729 reg = <0x2 0x3b700000 0 0x14000>;
734 reg = <0x2 0x3c100000 0x0 0x100000>;
739 gpio-ranges = <&pinctrl_ap 0 0 212>;
807 reg = <0x2 0x3d0d9300 0x0 0x100>;
809 #size-cells = <0>;
813 reg = <0xf SPMI_USID>;
821 reg = <0x9f01 0x1>;
824 boot_error_count: boot-error-count@9f02,0 {
825 reg = <0x9f02 0x1>;
826 bits = <0 4>;
830 reg = <0x9f02 0x1>;
835 reg = <0x9f03 0x1>;
839 reg = <0x9f0f 0x1>;
844 reg = <0xa67b 0x10>;
848 reg = <0xab00 0x400>;
852 reg = <0xd001 0x1>;
856 reg = <0xd100 0x6>;
864 reg = <0x2 0x3d1f0000 0x0 0x4000>;
869 gpio-ranges = <&pinctrl_nub 0 0 23>;
888 reg = <0x2 0x3d280000 0 0x4000>;
893 reg = <0x2 0x3d2b0000 0x0 0x4000>;
901 reg = <0x2 0x3e820000 0x0 0x4000>;
905 gpio-ranges = <&pinctrl_smc 0 0 16>;
922 reg = <0x2 0x4a820000 0x0 0x4000>;
926 gpio-ranges = <&pinctrl_aop 0 0 42>;
943 reg = <0x2 0x77408000 0x0 0x4000>;
951 #mbox-cells = <0>;
957 reg = <0x2 0x7bc50000 0x0 0x10000>;
963 reg = <0x2 0x7bcc0000 0x0 0x40000>,
964 <0x2 0x77400000 0x0 0x4000>;
977 reg = <0x6 0x81008000 0x0 0x4000>;
986 reg = <0x6 0x82008000 0x0 0x4000>;
996 reg = <0x6 0x83008000 0x0 0x4000>;
1008 reg = <0x6 0x90000000 0x0 0x1000000>,
1009 <0x6 0x80000000 0x0 0x100000>,
1010 <0x6 0x81000000 0x0 0x4000>,
1011 <0x6 0x82000000 0x0 0x4000>,
1012 <0x6 0x83000000 0x0 0x4000>;
1025 iommu-map = <0x100 &pcie0_dart_0 1 1>,
1026 <0x200 &pcie0_dart_1 1 1>,
1027 <0x300 &pcie0_dart_2 1 1>;
1028 iommu-map-mask = <0xff00>;
1030 bus-range = <0 3>;
1033 ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>,
1034 <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>;
1037 pinctrl-0 = <&pcie_pins>;
1040 port00: pci@0,0 {
1042 reg = <0x0 0x0 0x0 0x0 0x0>;
1052 interrupt-map-mask = <0 0 0 7>;
1053 interrupt-map = <0 0 0 1 &port00 0 0 0 0>,
1054 <0 0 0 2 &port00 0 0 0 1>,
1055 <0 0 0 3 &port00 0 0 0 2>,
1056 <0 0 0 4 &port00 0 0 0 3>;
1059 port01: pci@1,0 {
1061 reg = <0x800 0x0 0x0 0x0 0x0>;
1071 interrupt-map-mask = <0 0 0 7>;
1072 interrupt-map = <0 0 0 1 &port01 0 0 0 0>,
1073 <0 0 0 2 &port01 0 0 0 1>,
1074 <0 0 0 3 &port01 0 0 0 2>,
1075 <0 0 0 4 &port01 0 0 0 3>;
1079 port02: pci@2,0 {
1081 reg = <0x1000 0x0 0x0 0x0 0x0>;
1091 interrupt-map-mask = <0 0 0 7>;
1092 interrupt-map = <0 0 0 1 &port02 0 0 0 0>,
1093 <0 0 0 2 &port02 0 0 0 1>,
1094 <0 0 0 3 &port02 0 0 0 2>,
1095 <0 0 0 4 &port02 0 0 0 3>;