Lines Matching +full:opp +full:- +full:2
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
16 interrupt-parent = <&aic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
20 clkref: clock-ref {
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <24000000>;
24 clock-output-names = "clkref";
28 #address-cells = <2>;
29 #size-cells = <0>;
31 cpu-map {
60 cpu-release-addr = <0 0>; /* To be filled by loader */
61 performance-domains = <&cpufreq_e>;
62 operating-points-v2 = <&mistral_opp>;
63 capacity-dmips-mhz = <633>;
64 enable-method = "spin-table";
66 next-level-cache = <&l2_cache_0>;
67 i-cache-size = <0x8000>;
68 d-cache-size = <0x8000>;
74 cpu-release-addr = <0 0>; /* To be filled by loader */
75 performance-domains = <&cpufreq_e>;
76 operating-points-v2 = <&mistral_opp>;
77 capacity-dmips-mhz = <633>;
78 enable-method = "spin-table";
80 next-level-cache = <&l2_cache_0>;
81 i-cache-size = <0x8000>;
82 d-cache-size = <0x8000>;
85 cpu_e2: cpu@2 {
88 cpu-release-addr = <0 0>; /* To be filled by loader */
89 performance-domains = <&cpufreq_e>;
90 operating-points-v2 = <&mistral_opp>;
91 capacity-dmips-mhz = <633>;
92 enable-method = "spin-table";
94 next-level-cache = <&l2_cache_0>;
95 i-cache-size = <0x8000>;
96 d-cache-size = <0x8000>;
102 cpu-release-addr = <0 0>; /* To be filled by loader */
103 performance-domains = <&cpufreq_e>;
104 operating-points-v2 = <&mistral_opp>;
105 capacity-dmips-mhz = <633>;
106 enable-method = "spin-table";
108 next-level-cache = <&l2_cache_0>;
109 i-cache-size = <0x8000>;
110 d-cache-size = <0x8000>;
116 cpu-release-addr = <0 0>; /* To be filled by loader */
117 performance-domains = <&cpufreq_p>;
118 operating-points-v2 = <&monsoon_opp>;
119 capacity-dmips-mhz = <1024>;
120 enable-method = "spin-table";
122 next-level-cache = <&l2_cache_1>;
123 i-cache-size = <0x10000>;
124 d-cache-size = <0x10000>;
130 cpu-release-addr = <0 0>; /* To be filled by loader */
131 performance-domains = <&cpufreq_p>;
132 operating-points-v2 = <&monsoon_opp>;
133 capacity-dmips-mhz = <1024>;
134 enable-method = "spin-table";
136 next-level-cache = <&l2_cache_1>;
137 i-cache-size = <0x10000>;
138 d-cache-size = <0x10000>;
141 l2_cache_0: l2-cache-0 {
143 cache-level = <2>;
144 cache-unified;
145 cache-size = <0x100000>;
148 l2_cache_1: l2-cache-1 {
150 cache-level = <2>;
151 cache-unified;
152 cache-size = <0x800000>;
156 mistral_opp: opp-table-0 {
157 compatible = "operating-points-v2";
160 opp-hz = /bits/ 64 <300000000>;
161 opp-level = <1>;
162 clock-latency-ns = <1800>;
165 opp-hz = /bits/ 64 <453000000>;
166 opp-level = <2>;
167 clock-latency-ns = <140000>;
170 opp-hz = /bits/ 64 <672000000>;
171 opp-level = <3>;
172 clock-latency-ns = <105000>;
175 opp-hz = /bits/ 64 <972000000>;
176 opp-level = <4>;
177 clock-latency-ns = <115000>;
180 opp-hz = /bits/ 64 <1272000000>;
181 opp-level = <5>;
182 clock-latency-ns = <125000>;
185 opp-hz = /bits/ 64 <1572000000>;
186 opp-level = <6>;
187 clock-latency-ns = <135000>;
192 opp-hz = /bits/ 64 <1680000000>;
193 opp-level = <7>;
194 clock-latency-ns = <135000>;
195 turbo-mode;
200 monsoon_opp: opp-table-1 {
201 compatible = "operating-points-v2";
204 opp-hz = /bits/ 64 <300000000>;
205 opp-level = <1>;
206 clock-latency-ns = <1400>;
209 opp-hz = /bits/ 64 <453000000>;
210 opp-level = <2>;
211 clock-latency-ns = <140000>;
214 opp-hz = /bits/ 64 <853000000>;
215 opp-level = <3>;
216 clock-latency-ns = <110000>;
219 opp-hz = /bits/ 64 <1332000000>;
220 opp-level = <4>;
221 clock-latency-ns = <110000>;
224 opp-hz = /bits/ 64 <1812000000>;
225 opp-level = <5>;
226 clock-latency-ns = <125000>;
229 opp-hz = /bits/ 64 <2064000000>;
230 opp-level = <6>;
231 clock-latency-ns = <130000>;
234 opp-hz = /bits/ 64 <2304000000>;
235 opp-level = <7>;
236 clock-latency-ns = <140000>;
241 opp-hz = /bits/ 64 <2376000000>;
242 opp-level = <8>;
243 clock-latency-ns = <140000>;
244 turbo-mode;
250 compatible = "simple-bus";
251 #address-cells = <2>;
252 #size-cells = <2>;
253 nonposted-mmio;
256 cpufreq_e: performance-controller@208e20000 {
257 …compatible = "apple,t8015-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
259 #performance-domain-cells = <0>;
262 cpufreq_p: performance-controller@208ea0000 {
263 …compatible = "apple,t8015-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
265 #performance-domain-cells = <0>;
269 compatible = "apple,s5l-uart";
271 reg-io-width = <4>;
272 interrupt-parent = <&aic>;
274 /* Use the bootloader-enabled clocks for now. */
276 clock-names = "uart", "clk_uart_baud0";
277 power-domains = <&ps_uart0>;
281 aic: interrupt-controller@232100000 {
282 compatible = "apple,t8015-aic", "apple,aic";
284 #interrupt-cells = <3>;
285 interrupt-controller;
286 power-domains = <&ps_aic>;
289 pmgr: power-management@232000000 {
290 compatible = "apple,t8015-pmgr", "apple,pmgr", "syscon", "simple-mfd";
291 #address-cells = <1>;
292 #size-cells = <1>;
298 compatible = "apple,t8015-dwi-bl", "apple,dwi-bl";
300 power-domains = <&ps_dwi>;
305 compatible = "apple,t8015-pinctrl", "apple,pinctrl";
307 power-domains = <&ps_gpio>;
309 gpio-controller;
310 #gpio-cells = <2>;
311 gpio-ranges = <&pinctrl_ap 0 0 223>;
314 interrupt-controller;
315 #interrupt-cells = <2>;
316 interrupt-parent = <&aic>;
327 compatible = "apple,t8015-pinctrl", "apple,pinctrl";
330 gpio-controller;
331 #gpio-cells = <2>;
332 gpio-ranges = <&pinctrl_aop 0 0 49>;
335 interrupt-controller;
336 #interrupt-cells = <2>;
337 interrupt-parent = <&aic>;
348 compatible = "apple,t8015-pinctrl", "apple,pinctrl";
351 gpio-controller;
352 #gpio-cells = <2>;
353 gpio-ranges = <&pinctrl_nub 0 0 8>;
356 interrupt-controller;
357 #interrupt-cells = <2>;
358 interrupt-parent = <&aic>;
364 pmgr_mini: power-management@235200000 {
365 compatible = "apple,t8015-pmgr", "apple,pmgr", "syscon", "simple-mfd";
366 #address-cells = <1>;
367 #size-cells = <1>;
373 compatible = "apple,t8015-wdt", "apple,wdt";
376 interrupt-parent = <&aic>;
381 compatible = "apple,t8015-pinctrl", "apple,pinctrl";
384 gpio-controller;
385 #gpio-cells = <2>;
386 gpio-ranges = <&pinctrl_smc 0 0 6>;
389 interrupt-controller;
390 #interrupt-cells = <2>;
391 interrupt-parent = <&aic>;
408 compatible = "arm,armv8-timer";
409 interrupt-parent = <&aic>;
410 interrupt-names = "phys", "virt";
417 #include "t8015-pmgr.dtsi"