Lines Matching +full:supported +full:- +full:frequencies +full:- +full:hz
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
16 interrupt-parent = <&aic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
20 clkref: clock-ref {
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <24000000>;
24 clock-output-names = "clkref";
28 #address-cells = <2>;
29 #size-cells = <0>;
32 compatible = "apple,hurricane-zephyr";
34 cpu-release-addr = <0 0>; /* To be filled by loader */
35 operating-points-v2 = <&fusion_opp>;
36 performance-domains = <&cpufreq>;
37 enable-method = "spin-table";
39 next-level-cache = <&l2_cache>;
40 i-cache-size = <0x10000>; /* P-core */
41 d-cache-size = <0x10000>; /* P-core */
45 compatible = "apple,hurricane-zephyr";
47 cpu-release-addr = <0 0>; /* To be filled by loader */
48 operating-points-v2 = <&fusion_opp>;
49 performance-domains = <&cpufreq>;
50 enable-method = "spin-table";
52 next-level-cache = <&l2_cache>;
53 i-cache-size = <0x10000>; /* P-core */
54 d-cache-size = <0x10000>; /* P-core */
57 l2_cache: l2-cache {
59 cache-level = <2>;
60 cache-unified;
61 cache-size = <0x300000>; /* P-cluster */
65 fusion_opp: opp-table {
66 compatible = "operating-points-v2";
70 * that use p-state transitions to switch between cores.
73 * The E-core frequencies are adjusted so performance scales
78 opp-hz = /bits/ 64 <172000000>; /* 300 MHz, E-core */
79 opp-level = <1>;
80 clock-latency-ns = <11000>;
83 opp-hz = /bits/ 64 <230000000>; /* 396 MHz, E-core */
84 opp-level = <2>;
85 clock-latency-ns = <140000>;
88 opp-hz = /bits/ 64 <425000000>; /* 732 MHz, E-core */
89 opp-level = <3>;
90 clock-latency-ns = <110000>;
93 opp-hz = /bits/ 64 <637000000>; /* 1092 MHz, E-core */
94 opp-level = <4>;
95 clock-latency-ns = <130000>;
98 opp-hz = /bits/ 64 <756000000>;
99 opp-level = <5>;
100 clock-latency-ns = <130000>;
103 opp-hz = /bits/ 64 <1056000000>;
104 opp-level = <6>;
105 clock-latency-ns = <130000>;
108 opp-hz = /bits/ 64 <1356000000>;
109 opp-level = <7>;
110 clock-latency-ns = <130000>;
113 opp-hz = /bits/ 64 <1644000000>;
114 opp-level = <8>;
115 clock-latency-ns = <135000>;
118 opp-hz = /bits/ 64 <1944000000>;
119 opp-level = <9>;
120 clock-latency-ns = <140000>;
123 opp-hz = /bits/ 64 <2244000000>;
124 opp-level = <10>;
125 clock-latency-ns = <150000>;
130 opp-hz = /bits/ 64 <2340000000>;
131 opp-level = <11>;
132 clock-latency-ns = <150000>;
133 turbo-mode;
139 compatible = "simple-bus";
140 #address-cells = <2>;
141 #size-cells = <2>;
142 nonposted-mmio;
145 cpufreq: performance-controller@202f20000 {
146 …compatible = "apple,t8010-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
148 #performance-domain-cells = <0>;
152 compatible = "apple,s5l-uart";
154 reg-io-width = <4>;
155 interrupt-parent = <&aic>;
157 /* Use the bootloader-enabled clocks for now. */
159 clock-names = "uart", "clk_uart_baud0";
160 power-domains = <&ps_uart0>;
164 pmgr: power-management@20e000000 {
165 compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd";
166 #address-cells = <1>;
167 #size-cells = <1>;
172 aic: interrupt-controller@20e100000 {
173 compatible = "apple,t8010-aic", "apple,aic";
175 #interrupt-cells = <3>;
176 interrupt-controller;
177 power-domains = <&ps_aic>;
181 compatible = "apple,t8010-pinctrl", "apple,pinctrl";
183 power-domains = <&ps_gpio>;
185 gpio-controller;
186 #gpio-cells = <2>;
187 gpio-ranges = <&pinctrl_ap 0 0 221>;
190 interrupt-controller;
191 #interrupt-cells = <2>;
192 interrupt-parent = <&aic>;
203 compatible = "apple,t8010-pinctrl", "apple,pinctrl";
206 gpio-controller;
207 #gpio-cells = <2>;
208 gpio-ranges = <&pinctrl_aop 0 0 41>;
211 interrupt-controller;
212 #interrupt-cells = <2>;
213 interrupt-parent = <&aic>;
224 compatible = "apple,t8010-pinctrl", "apple,pinctrl";
227 gpio-controller;
228 #gpio-cells = <2>;
229 gpio-ranges = <&pinctrl_nub 0 0 19>;
232 interrupt-controller;
233 #interrupt-cells = <2>;
234 interrupt-parent = <&aic>;
240 pmgr_mini: power-management@211200000 {
241 compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd";
242 #address-cells = <1>;
243 #size-cells = <1>;
249 compatible = "apple,t8010-wdt", "apple,wdt";
252 interrupt-parent = <&aic>;
257 compatible = "apple,t8010-pinctrl", "apple,pinctrl";
259 power-domains = <&ps_smc_cpu>;
261 gpio-controller;
262 #gpio-cells = <2>;
263 gpio-ranges = <&pinctrl_smc 0 0 81>;
266 interrupt-controller;
267 #interrupt-cells = <2>;
268 interrupt-parent = <&aic>;
277 * SMC is not yet supported and accessing this pinctrl while SMC is
285 compatible = "arm,armv8-timer";
286 interrupt-parent = <&aic>;
287 interrupt-names = "phys", "virt";
294 #include "t8012-pmgr.dtsi"