Lines Matching +full:s5l +full:- +full:fpwm
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 nco: clock-controller@28e03c000 {
11 compatible = "apple,t6000-nco", "apple,nco";
14 #clock-cells = <1>;
17 aic: interrupt-controller@28e100000 {
18 compatible = "apple,t6000-aic", "apple,aic2";
19 #interrupt-cells = <4>;
20 interrupt-controller;
23 reg-names = "core", "event";
24 power-domains = <&ps_aic>;
28 compatible = "apple,t6000-pinctrl", "apple,pinctrl";
31 gpio-controller;
32 #gpio-cells = <2>;
33 gpio-ranges = <&pinctrl_smc 0 0 30>;
36 interrupt-controller;
37 #interrupt-cells = <2>;
38 interrupt-parent = <&aic>;
49 compatible = "apple,t6000-wdt", "apple,wdt";
52 interrupt-parent = <&aic>;
57 compatible = "apple,t6000-dart";
59 interrupt-parent = <&aic>;
61 #iommu-cells = <1>;
62 power-domains = <&ps_sio_cpu>;
66 compatible = "apple,t6000-dart";
68 interrupt-parent = <&aic>;
70 #iommu-cells = <1>;
71 power-domains = <&ps_sio_cpu>;
75 compatible = "apple,t6000-fpwm", "apple,s5l-fpwm";
77 power-domains = <&ps_fpwm0>;
79 #pwm-cells = <2>;
84 compatible = "apple,t6000-i2c", "apple,i2c";
87 interrupt-parent = <&aic>;
89 pinctrl-0 = <&i2c0_pins>;
90 pinctrl-names = "default";
91 power-domains = <&ps_i2c0>;
92 #address-cells = <0x1>;
93 #size-cells = <0x0>;
97 compatible = "apple,t6000-i2c", "apple,i2c";
100 interrupt-parent = <&aic>;
102 pinctrl-0 = <&i2c1_pins>;
103 pinctrl-names = "default";
104 power-domains = <&ps_i2c1>;
105 #address-cells = <0x1>;
106 #size-cells = <0x0>;
111 compatible = "apple,t6000-i2c", "apple,i2c";
114 interrupt-parent = <&aic>;
116 pinctrl-0 = <&i2c2_pins>;
117 pinctrl-names = "default";
118 power-domains = <&ps_i2c2>;
119 #address-cells = <0x1>;
120 #size-cells = <0x0>;
125 compatible = "apple,t6000-i2c", "apple,i2c";
128 interrupt-parent = <&aic>;
130 pinctrl-0 = <&i2c3_pins>;
131 pinctrl-names = "default";
132 power-domains = <&ps_i2c3>;
133 #address-cells = <0x1>;
134 #size-cells = <0x0>;
139 compatible = "apple,t6000-i2c", "apple,i2c";
142 interrupt-parent = <&aic>;
144 pinctrl-0 = <&i2c4_pins>;
145 pinctrl-names = "default";
146 power-domains = <&ps_i2c4>;
147 #address-cells = <0x1>;
148 #size-cells = <0x0>;
153 compatible = "apple,t6000-i2c", "apple,i2c";
156 interrupt-parent = <&aic>;
158 pinctrl-0 = <&i2c5_pins>;
159 pinctrl-names = "default";
160 power-domains = <&ps_i2c5>;
161 #address-cells = <0x1>;
162 #size-cells = <0x0>;
167 compatible = "apple,t6000-spi", "apple,spi";
169 interrupt-parent = <&aic>;
171 #address-cells = <1>;
172 #size-cells = <0>;
174 pinctrl-0 = <&spi1_pins>;
175 pinctrl-names = "default";
176 power-domains = <&ps_spi1>;
181 compatible = "apple,t6000-spi", "apple,spi";
183 interrupt-parent = <&aic>;
185 #address-cells = <1>;
186 #size-cells = <0>;
188 pinctrl-0 = <&spi3_pins>;
189 pinctrl-names = "default";
190 power-domains = <&ps_spi3>;
195 compatible = "apple,s5l-uart";
197 reg-io-width = <4>;
198 interrupt-parent = <&aic>;
205 clock-names = "uart", "clk_uart_baud0";
206 power-domains = <&ps_uart0>;
210 admac: dma-controller@39b400000 {
211 compatible = "apple,t6000-admac", "apple,admac";
213 #dma-cells = <1>;
214 dma-channels = <16>;
215 interrupts-extended = <0>,
220 power-domains = <&ps_sio_adma>;
225 compatible = "apple,t6000-mca", "apple,mca";
233 dma-names = "tx0a", "rx0a", "tx0b", "rx0b",
237 interrupt-parent = <&aic>;
242 power-domains = <&ps_audio_p>, <&ps_mca0>, <&ps_mca1>,
245 #sound-dai-cells = <1>;
249 compatible = "apple,t6000-dart";
251 #iommu-cells = <1>;
252 interrupt-parent = <&aic>;
254 power-domains = <&ps_apcie_gp_sys>;
258 compatible = "apple,t6000-dart";
260 #iommu-cells = <1>;
261 interrupt-parent = <&aic>;
263 power-domains = <&ps_apcie_gp_sys>;
267 compatible = "apple,t6000-dart";
269 #iommu-cells = <1>;
270 interrupt-parent = <&aic>;
272 power-domains = <&ps_apcie_gp_sys>;
277 compatible = "apple,t6000-dart";
279 #iommu-cells = <1>;
280 interrupt-parent = <&aic>;
282 power-domains = <&ps_apcie_gp_sys>;
287 compatible = "apple,t6000-pcie", "apple,pcie";
296 reg-names = "config", "rc", "port0", "port1", "port2", "port3";
298 interrupt-parent = <&aic>;
304 msi-controller;
305 msi-parent = <&pcie0>;
306 msi-ranges = <&aic AIC_IRQ 0 1581 IRQ_TYPE_EDGE_RISING 32>;
309 iommu-map = <0x100 &pcie0_dart_0 1 1>,
313 iommu-map-mask = <0xff00>;
315 bus-range = <0 4>;
316 #address-cells = <3>;
317 #size-cells = <2>;
321 power-domains = <&ps_apcie_gp_sys>;
322 pinctrl-0 = <&pcie_pins>;
323 pinctrl-names = "default";
328 reset-gpios = <&pinctrl_ap 4 GPIO_ACTIVE_LOW>;
330 #address-cells = <3>;
331 #size-cells = <2>;
334 interrupt-controller;
335 #interrupt-cells = <1>;
337 interrupt-map-mask = <0 0 0 7>;
338 interrupt-map = <0 0 0 1 &port00 0 0 0 0>,
347 reset-gpios = <&pinctrl_ap 5 GPIO_ACTIVE_LOW>;
349 #address-cells = <3>;
350 #size-cells = <2>;
353 interrupt-controller;
354 #interrupt-cells = <1>;
356 interrupt-map-mask = <0 0 0 7>;
357 interrupt-map = <0 0 0 1 &port01 0 0 0 0>,
366 reset-gpios = <&pinctrl_ap 6 GPIO_ACTIVE_LOW>;
368 #address-cells = <3>;
369 #size-cells = <2>;
372 interrupt-controller;
373 #interrupt-cells = <1>;
375 interrupt-map-mask = <0 0 0 7>;
376 interrupt-map = <0 0 0 1 &port02 0 0 0 0>,
386 reset-gpios = <&pinctrl_ap 7 GPIO_ACTIVE_LOW>;
388 #address-cells = <3>;
389 #size-cells = <2>;
392 interrupt-controller;
393 #interrupt-cells = <1>;
395 interrupt-map-mask = <0 0 0 7>;
396 interrupt-map = <0 0 0 1 &port03 0 0 0 0>,