Lines Matching +full:bias +full:- +full:disable
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-gx.dtsi"
8 #include <dt-bindings/clock/gxbb-clkc.h>
9 #include <dt-bindings/clock/gxbb-aoclkc.h>
10 #include <dt-bindings/gpio/meson-gxl-gpio.h>
11 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
14 compatible = "amlogic,meson-gxl";
18 compatible = "amlogic,meson-gxl-usb-ctrl";
21 #address-cells = <2>;
22 #size-cells = <2>;
26 clock-names = "usb_ctrl", "ddr";
32 phy-names = "usb2-phy0", "usb2-phy1";
35 compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
39 clock-names = "otg";
42 g-rx-fifo-size = <192>;
43 g-np-tx-fifo-size = <128>;
44 g-tx-fifo-size = <128 128 16 16 16>;
52 maximum-speed = "high-speed";
57 acodec: audio-controller@c8832000 {
60 #sound-dai-cells = <0>;
61 sound-name-prefix = "ACODEC";
63 clock-names = "pclk";
69 compatible = "amlogic,gxl-crypto";
74 clock-names = "blkmv";
81 compatible = "amlogic,aiu-gxl", "amlogic,aiu";
91 clock-names = "pclk",
105 compatible = "amlogic,meson-gxl-usb2-phy";
106 #phy-cells = <0>;
109 clock-names = "phy";
111 reset-names = "phy";
116 compatible = "amlogic,meson-gxl-usb2-phy";
117 #phy-cells = <0>;
120 clock-names = "phy";
122 reset-names = "phy";
136 clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
139 #address-cells = <1>;
140 #size-cells = <0>;
141 compatible = "snps,dwmac-mdio";
147 compatible = "amlogic,meson-gxl-aobus-pinctrl";
148 #address-cells = <2>;
149 #size-cells = <2>;
156 reg-names = "mux", "pull", "gpio";
157 gpio-controller;
158 #gpio-cells = <2>;
159 gpio-ranges = <&pinctrl_aobus 0 0 14>;
166 bias-disable;
175 bias-disable;
183 bias-disable;
191 bias-disable;
200 bias-disable;
208 bias-disable;
217 bias-disable;
225 bias-disable;
233 bias-disable;
241 bias-disable;
249 bias-disable;
257 bias-disable;
265 bias-disable;
273 bias-disable;
281 bias-disable;
289 bias-disable;
297 bias-disable;
305 clock-names = "core";
309 compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
311 clock-names = "xtal", "mpeg-clk";
315 compatible = "amlogic,meson-gxl-gpio-intc",
316 "amlogic,meson-gpio-intc";
321 compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
325 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
329 clock-names = "isfr", "iahb", "venci";
330 power-domains = <&pwrc PWRC_GXBB_VPU_ID>;
332 assigned-clocks = <&clkc CLKID_HDMI_SEL>,
334 assigned-clock-parents = <&xtal>, <0>;
335 assigned-clock-rates = <0>, <24000000>;
339 clkc: clock-controller {
340 compatible = "amlogic,gxl-clkc";
341 #clock-cells = <1>;
343 clock-names = "xtal";
349 clock-names = "core";
370 compatible = "amlogic,meson-gxl-periphs-pinctrl";
371 #address-cells = <2>;
372 #size-cells = <2>;
380 reg-names = "mux", "pull", "pull-enable", "gpio";
381 gpio-controller;
382 #gpio-cells = <2>;
383 gpio-ranges = <&pinctrl_periphs 0 0 100>;
387 mux-0 {
391 bias-pull-up;
394 mux-1 {
397 bias-disable;
401 emmc_ds_pins: emmc-ds {
405 bias-pull-down;
413 bias-pull-down;
424 bias-disable;
428 spi_pins: spi-pins {
434 bias-disable;
438 spi_idle_high_pins: spi-idle-high-pins {
441 bias-pull-up;
445 spi_idle_low_pins: spi-idle-low-pins {
448 bias-pull-down;
452 spi_ss0_pins: spi-ss0 {
456 bias-disable;
461 mux-0 {
468 bias-pull-up;
471 mux-1 {
474 bias-disable;
482 bias-pull-down;
487 mux-0 {
494 bias-pull-up;
497 mux-1 {
500 bias-disable;
508 bias-pull-down;
516 bias-disable;
525 bias-disable;
534 bias-disable;
543 bias-disable;
552 bias-disable;
561 bias-disable;
570 bias-disable;
579 bias-disable;
588 bias-disable;
597 bias-disable;
606 bias-disable;
627 bias-disable;
635 bias-disable;
650 bias-disable;
658 bias-disable;
666 bias-disable;
674 bias-disable;
682 bias-disable;
690 bias-disable;
698 bias-disable;
706 bias-disable;
714 bias-disable;
722 bias-disable;
730 bias-disable;
738 bias-disable;
746 bias-disable;
753 bias-disable;
761 bias-disable;
769 bias-disable;
777 bias-disable;
784 compatible = "amlogic,gxl-mdio-mux";
785 #address-cells = <1>;
786 #size-cells = <0>;
788 clock-names = "ref";
789 mdio-parent-bus = <&mdio0>;
793 #address-cells = <1>;
794 #size-cells = <0>;
799 #address-cells = <1>;
800 #size-cells = <0>;
802 internal_phy: ethernet-phy@8 {
803 compatible = "ethernet-phy-id0181.4400";
806 max-speed = <100>;
825 reset-names = "viu", "venc", "vcbus", "bt656",
830 clock-names = "vpu", "vapb";
837 assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
843 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
849 assigned-clock-rates = <0>, /* Do Nothing */
858 compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
863 clock-names = "clkin", "core", "adc_clk", "adc_sel";
870 clock-names = "core", "clkin0", "clkin1";
878 clock-names = "core", "clkin0", "clkin1";
886 clock-names = "core", "clkin0", "clkin1";
898 clock-names = "core";
900 num-cs = <1>;
909 clock-names = "xtal", "pclk", "baud";
914 clock-names = "xtal", "pclk", "baud";
919 clock-names = "xtal", "pclk", "baud";
924 clock-names = "xtal", "pclk", "baud";
929 clock-names = "xtal", "pclk", "baud";
933 compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
934 power-domains = <&pwrc PWRC_GXBB_VPU_ID>;
938 compatible = "amlogic,gxl-vdec", "amlogic,gx-vdec";
943 clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc";
945 reset-names = "esparser";