Lines Matching +full:d +full:- +full:cache +full:- +full:sets
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-g12.dtsi"
13 #address-cells = <0x2>;
14 #size-cells = <0x0>;
16 cpu-map {
48 compatible = "arm,cortex-a53";
50 enable-method = "psci";
51 capacity-dmips-mhz = <592>;
52 d-cache-line-size = <32>;
53 d-cache-size = <0x8000>;
54 d-cache-sets = <32>;
55 i-cache-line-size = <32>;
56 i-cache-size = <0x8000>;
57 i-cache-sets = <32>;
58 next-level-cache = <&l2_cache_l>;
59 #cooling-cells = <2>;
64 compatible = "arm,cortex-a53";
66 enable-method = "psci";
67 capacity-dmips-mhz = <592>;
68 d-cache-line-size = <32>;
69 d-cache-size = <0x8000>;
70 d-cache-sets = <32>;
71 i-cache-line-size = <32>;
72 i-cache-size = <0x8000>;
73 i-cache-sets = <32>;
74 next-level-cache = <&l2_cache_l>;
75 #cooling-cells = <2>;
80 compatible = "arm,cortex-a73";
82 enable-method = "psci";
83 capacity-dmips-mhz = <1024>;
84 d-cache-line-size = <32>;
85 d-cache-size = <0x8000>;
86 d-cache-sets = <32>;
87 i-cache-line-size = <32>;
88 i-cache-size = <0x8000>;
89 i-cache-sets = <32>;
90 next-level-cache = <&l2_cache_b>;
91 #cooling-cells = <2>;
96 compatible = "arm,cortex-a73";
98 enable-method = "psci";
99 capacity-dmips-mhz = <1024>;
100 d-cache-line-size = <32>;
101 d-cache-size = <0x8000>;
102 d-cache-sets = <32>;
103 i-cache-line-size = <32>;
104 i-cache-size = <0x8000>;
105 i-cache-sets = <32>;
106 next-level-cache = <&l2_cache_b>;
107 #cooling-cells = <2>;
112 compatible = "arm,cortex-a73";
114 enable-method = "psci";
115 capacity-dmips-mhz = <1024>;
116 d-cache-line-size = <64>;
117 d-cache-size = <0x10000>;
118 d-cache-sets = <64>;
119 i-cache-line-size = <64>;
120 i-cache-size = <0x10000>;
121 i-cache-sets = <64>;
122 next-level-cache = <&l2_cache_b>;
123 #cooling-cells = <2>;
128 compatible = "arm,cortex-a73";
130 enable-method = "psci";
131 capacity-dmips-mhz = <1024>;
132 d-cache-line-size = <64>;
133 d-cache-size = <0x10000>;
134 d-cache-sets = <64>;
135 i-cache-line-size = <64>;
136 i-cache-size = <0x10000>;
137 i-cache-sets = <64>;
138 next-level-cache = <&l2_cache_b>;
139 #cooling-cells = <2>;
142 l2_cache_l: l2-cache-cluster0 {
143 compatible = "cache";
144 cache-level = <2>;
145 cache-unified;
146 cache-size = <0x40000>; /* L2. 256 KB */
147 cache-line-size = <64>;
148 cache-sets = <512>;
151 l2_cache_b: l2-cache-cluster1 {
152 compatible = "cache";
153 cache-level = <2>;
154 cache-unified;
155 cache-size = <0x100000>; /* L2. 1MB */
156 cache-line-size = <64>;
157 cache-sets = <512>;
163 compatible = "amlogic,g12b-clkc";
167 cooling-maps {
170 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
179 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
190 dma-coherent;
194 compatible = "amlogic,g12b-ddr-pmu";
198 power-domains = <&pwrc PWRC_G12A_NNA_ID>;