Lines Matching +full:reg +full:- +full:spacing
1 // SPDX-License-Identifier: GPL-2.0
10 interrupt-parent = <&gic0>;
11 #address-cells = <2>;
12 #size-cells = <2>;
14 gic0: interrupt-controller@e1101000 {
15 compatible = "arm,gic-400", "arm,cortex-a15-gic";
16 interrupt-controller;
17 #interrupt-cells = <3>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20 reg = <0x0 0xe1110000 0 0x1000>,
27 compatible = "arm,gic-v2m-frame";
28 msi-controller;
29 reg = <0x0 0x00080000 0 0x1000>;
34 compatible = "arm,armv8-timer";
42 compatible = "simple-bus";
43 #address-cells = <2>;
44 #size-cells = <2>;
48 * dma-ranges is 40-bit address space containing:
49 * - GICv2m MSI register is at 0xe0080000
50 * - DRAM range [0x8000000000 to 0xffffffffff]
52 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
54 /include/ "amd-seattle-clks.dtsi"
57 compatible = "snps,dwc-ahci";
58 reg = <0 0xe0300000 0 0xf0000>;
62 dma-coherent;
68 compatible = "snps,dwc-ahci";
69 reg = <0 0xe0d00000 0 0xf0000>;
75 dma-coherent;
79 compatible = "arm,mmu-401";
80 reg = <0 0xe0200000 0 0x10000>;
81 #global-interrupts = <1>;
83 #iommu-cells = <2>;
84 dma-coherent;
88 compatible = "arm,mmu-401";
89 reg = <0 0xe0c00000 0 0x10000>;
90 #global-interrupts = <1>;
92 #iommu-cells = <1>;
93 dma-coherent;
98 compatible = "snps,designware-i2c";
99 reg = <0 0xe1000000 0 0x1000>;
106 compatible = "snps,designware-i2c";
107 reg = <0 0xe0050000 0 0x1000>;
114 reg = <0 0xe1010000 0 0x1000>;
117 clock-names = "uartclk", "apb_pclk";
123 reg = <0 0xe1020000 0 0x1000>;
124 spi-controller;
127 clock-names = "apb_pclk";
133 reg = <0 0xe1030000 0 0x1000>;
134 spi-controller;
137 clock-names = "apb_pclk";
138 num-cs = <1>;
139 #address-cells = <1>;
140 #size-cells = <0>;
146 #gpio-cells = <2>;
147 reg = <0 0xe1040000 0 0x1000>;
148 gpio-controller;
150 interrupt-controller;
151 #interrupt-cells = <2>;
153 clock-names = "apb_pclk";
159 #gpio-cells = <2>;
160 reg = <0 0xe1050000 0 0x1000>;
161 gpio-controller;
162 interrupt-controller;
163 #interrupt-cells = <2>;
166 clock-names = "apb_pclk";
172 #gpio-cells = <2>;
173 reg = <0 0xe0020000 0 0x1000>;
174 gpio-controller;
175 interrupt-controller;
176 #interrupt-cells = <2>;
179 clock-names = "apb_pclk";
185 #gpio-cells = <2>;
186 reg = <0 0xe0030000 0 0x1000>;
187 gpio-controller;
188 interrupt-controller;
189 #interrupt-cells = <2>;
192 clock-names = "apb_pclk";
198 #gpio-cells = <2>;
199 reg = <0 0xe0080000 0 0x1000>;
200 gpio-controller;
201 interrupt-controller;
202 #interrupt-cells = <2>;
205 clock-names = "apb_pclk";
210 compatible = "amd,ccp-seattle-v1a";
211 reg = <0 0xe0100000 0 0x10000>;
213 dma-coherent;
221 compatible = "pci-host-ecam-generic";
222 #address-cells = <3>;
223 #size-cells = <2>;
224 #interrupt-cells = <1>;
226 bus-range = <0 0x7f>;
227 msi-parent = <&v2m0>;
228 reg = <0 0xf0000000 0 0x10000000>;
230 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
231 interrupt-map =
247 dma-coherent;
248 dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>;
252 /* 32-bit MMIO (size=2G) */
254 /* 64-bit MMIO (size= 508G) */
256 iommu-map = <0x0 &pcie_smmu 0x0 0x10000>;
260 compatible = "arm,mmu-401";
261 reg = <0 0xe0a00000 0 0x10000>;
262 #global-interrupts = <1>;
264 #iommu-cells = <1>;
265 dma-coherent;
270 compatible = "arm,ccn-504";
271 reg = <0x0 0xe8000000 0 0x1000000>;
277 compatible = "ipmi-kcs";
279 reg = <0x0 0xe0010000 0 0x8>;
281 reg-size = <1>;
282 reg-spacing = <4>;