Lines Matching +full:ccn +full:- +full:504
1 // SPDX-License-Identifier: GPL-2.0
10 interrupt-parent = <&gic0>;
11 #address-cells = <2>;
12 #size-cells = <2>;
14 /include/ "amd-seattle-clks.dtsi"
16 gic0: interrupt-controller@e1101000 {
17 compatible = "arm,gic-400", "arm,cortex-a15-gic";
18 interrupt-controller;
19 #interrupt-cells = <3>;
20 #address-cells = <2>;
21 #size-cells = <2>;
29 compatible = "arm,gic-v2m-frame";
30 msi-controller;
36 compatible = "arm,armv8-timer";
44 compatible = "simple-bus";
45 #address-cells = <2>;
46 #size-cells = <2>;
50 * dma-ranges is 40-bit address space containing:
51 * - GICv2m MSI register is at 0xe0080000
52 * - DRAM range [0x8000000000 to 0xffffffffff]
54 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
57 compatible = "snps,dwc-ahci";
62 dma-coherent;
68 compatible = "snps,dwc-ahci";
75 dma-coherent;
79 compatible = "arm,mmu-401";
81 #global-interrupts = <1>;
83 #iommu-cells = <2>;
84 dma-coherent;
88 compatible = "arm,mmu-401";
90 #global-interrupts = <1>;
92 #iommu-cells = <1>;
93 dma-coherent;
98 compatible = "snps,designware-i2c";
106 compatible = "snps,designware-i2c";
117 clock-names = "uartclk", "apb_pclk";
126 clock-names = "sspclk", "apb_pclk";
135 clock-names = "sspclk", "apb_pclk";
136 num-cs = <1>;
137 #address-cells = <1>;
138 #size-cells = <0>;
144 #gpio-cells = <2>;
146 gpio-controller;
148 interrupt-controller;
149 #interrupt-cells = <2>;
151 clock-names = "apb_pclk";
157 #gpio-cells = <2>;
159 gpio-controller;
160 interrupt-controller;
161 #interrupt-cells = <2>;
164 clock-names = "apb_pclk";
170 #gpio-cells = <2>;
172 gpio-controller;
173 interrupt-controller;
174 #interrupt-cells = <2>;
177 clock-names = "apb_pclk";
183 #gpio-cells = <2>;
185 gpio-controller;
186 interrupt-controller;
187 #interrupt-cells = <2>;
190 clock-names = "apb_pclk";
196 #gpio-cells = <2>;
198 gpio-controller;
199 interrupt-controller;
200 #interrupt-cells = <2>;
203 clock-names = "apb_pclk";
208 compatible = "amd,ccp-seattle-v1a";
211 dma-coherent;
219 compatible = "pci-host-ecam-generic";
220 #address-cells = <3>;
221 #size-cells = <2>;
222 #interrupt-cells = <1>;
224 bus-range = <0 0x7f>;
225 msi-parent = <&v2m0>;
228 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
229 interrupt-map =
245 dma-coherent;
246 dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>;
250 /* 32-bit MMIO (size=2G) */
252 /* 64-bit MMIO (size= 508G) */
254 iommu-map = <0x0 &pcie_smmu 0x0 0x10000>;
258 compatible = "arm,mmu-401";
260 #global-interrupts = <1>;
262 #iommu-cells = <1>;
263 dma-coherent;
267 ccn: ccn@e8000000 { label
268 compatible = "arm,ccn-504";
275 compatible = "ipmi-kcs";
279 reg-size = <1>;
280 reg-spacing = <4>;