Lines Matching +full:0 +full:x8000
5 #address-cells = <0x1>;
6 #size-cells = <0x0>;
43 CPU0: cpu@0 {
46 reg = <0x0>;
49 i-cache-size = <0xC000>;
52 d-cache-size = <0x8000>;
62 reg = <0x1>;
65 i-cache-size = <0xC000>;
68 d-cache-size = <0x8000>;
77 reg = <0x100>;
80 i-cache-size = <0xC000>;
83 d-cache-size = <0x8000>;
92 reg = <0x101>;
95 i-cache-size = <0xC000>;
98 d-cache-size = <0x8000>;
107 reg = <0x200>;
110 i-cache-size = <0xC000>;
113 d-cache-size = <0x8000>;
122 reg = <0x201>;
125 i-cache-size = <0xC000>;
128 d-cache-size = <0x8000>;
137 reg = <0x300>;
140 i-cache-size = <0xC000>;
143 d-cache-size = <0x8000>;
152 reg = <0x301>;
155 i-cache-size = <0xC000>;
158 d-cache-size = <0x8000>;
166 cache-size = <0x100000>;
174 cache-size = <0x100000>;
182 cache-size = <0x100000>;
190 cache-size = <0x100000>;
199 cache-size = <0x800000>;
207 interrupts = <0x0 0x7 0x4>,
208 <0x0 0x8 0x4>,
209 <0x0 0x9 0x4>,
210 <0x0 0xa 0x4>,
211 <0x0 0xb 0x4>,
212 <0x0 0xc 0x4>,
213 <0x0 0xd 0x4>,
214 <0x0 0xe 0x4>;