Lines Matching +full:sysmgr +full:- +full:syscon
1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
18 #size-cells = <2>;
22 compatible = "shared-dma-pool";
25 no-map;
30 #address-cells = <1>;
31 #size-cells = <0>;
34 compatible = "arm,cortex-a53";
36 enable-method = "psci";
37 next-level-cache = <&l2_shared>;
42 compatible = "arm,cortex-a53";
44 enable-method = "psci";
45 next-level-cache = <&l2_shared>;
50 compatible = "arm,cortex-a53";
52 enable-method = "psci";
53 next-level-cache = <&l2_shared>;
58 compatible = "arm,cortex-a53";
60 enable-method = "psci";
61 next-level-cache = <&l2_shared>;
67 cache-level = <2>;
68 cache-unified;
74 compatible = "intel,stratix10-svc";
76 memory-region = <&service_reserved>;
78 fpga_mgr: fpga-mgr {
79 compatible = "intel,stratix10-soc-fpga-mgr";
84 fpga-region {
85 compatible = "fpga-region";
86 #address-cells = <0x2>;
87 #size-cells = <0x2>;
88 fpga-mgr = <&fpga_mgr>;
92 compatible = "arm,cortex-a53-pmu";
97 interrupt-affinity = <&cpu0>,
101 interrupt-parent = <&intc>;
105 compatible = "arm,psci-0.2";
111 compatible = "arm,armv8-timer";
116 interrupt-parent = <&intc>;
119 intc: interrupt-controller@fffc1000 {
120 compatible = "arm,gic-400", "arm,cortex-a15-gic";
121 #interrupt-cells = <3>;
122 interrupt-controller;
130 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
131 #clock-cells = <0>;
132 compatible = "fixed-clock";
133 clock-frequency = <150000000>;
136 cb_intosc_ls_clk: cb-intosc-ls-clk {
137 #clock-cells = <0>;
138 compatible = "fixed-clock";
139 clock-frequency = <300000000>;
142 f2s_free_clk: f2s-free-clk {
143 #clock-cells = <0>;
144 compatible = "fixed-clock";
149 #clock-cells = <0>;
150 compatible = "fixed-clock";
153 qspi_clk: qspi-clk {
154 #clock-cells = <0>;
155 compatible = "fixed-clock";
156 clock-frequency = <200000000>;
161 #address-cells = <1>;
162 #size-cells = <1>;
163 compatible = "simple-bus";
165 interrupt-parent = <&intc>;
168 clkmgr: clock-controller@ffd10000 {
169 compatible = "intel,stratix10-clkmgr";
171 #clock-cells = <1>;
175 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
178 interrupt-names = "macirq";
179 mac-address = [00 00 00 00 00 00];
181 reset-names = "stmmaceth", "ahb";
183 clock-names = "stmmaceth", "ptp_ref";
184 tx-fifo-depth = <16384>;
185 rx-fifo-depth = <16384>;
186 snps,multicast-filter-bins = <256>;
188 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
193 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
196 interrupt-names = "macirq";
197 mac-address = [00 00 00 00 00 00];
199 reset-names = "stmmaceth", "ahb";
201 clock-names = "stmmaceth", "ptp_ref";
202 tx-fifo-depth = <16384>;
203 rx-fifo-depth = <16384>;
204 snps,multicast-filter-bins = <256>;
206 altr,sysmgr-syscon = <&sysmgr 0x48 8>;
211 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
214 interrupt-names = "macirq";
215 mac-address = [00 00 00 00 00 00];
217 reset-names = "stmmaceth", "ahb";
219 clock-names = "stmmaceth", "ptp_ref";
220 tx-fifo-depth = <16384>;
221 rx-fifo-depth = <16384>;
222 snps,multicast-filter-bins = <256>;
224 altr,sysmgr-syscon = <&sysmgr 0x4c 16>;
229 #address-cells = <1>;
230 #size-cells = <0>;
231 compatible = "snps,dw-apb-gpio";
236 porta: gpio-controller@0 {
237 compatible = "snps,dw-apb-gpio-port";
238 gpio-controller;
239 #gpio-cells = <2>;
242 interrupt-controller;
243 #interrupt-cells = <2>;
249 #address-cells = <1>;
250 #size-cells = <0>;
251 compatible = "snps,dw-apb-gpio";
256 portb: gpio-controller@0 {
257 compatible = "snps,dw-apb-gpio-port";
258 gpio-controller;
259 #gpio-cells = <2>;
262 interrupt-controller;
263 #interrupt-cells = <2>;
269 #address-cells = <1>;
270 #size-cells = <0>;
271 compatible = "snps,designware-i2c";
280 #address-cells = <1>;
281 #size-cells = <0>;
282 compatible = "snps,designware-i2c";
291 #address-cells = <1>;
292 #size-cells = <0>;
293 compatible = "snps,designware-i2c";
302 #address-cells = <1>;
303 #size-cells = <0>;
304 compatible = "snps,designware-i2c";
313 #address-cells = <1>;
314 #size-cells = <0>;
315 compatible = "snps,designware-i2c";
324 #address-cells = <1>;
325 #size-cells = <0>;
326 compatible = "altr,socfpga-dw-mshc";
329 fifo-depth = <0x400>;
331 reset-names = "reset";
334 clock-names = "biu", "ciu";
336 altr,sysmgr-syscon = <&sysmgr 0x28 4>;
340 nand: nand-controller@ffb90000 {
341 #address-cells = <1>;
342 #size-cells = <0>;
343 compatible = "altr,socfpga-denali-nand";
346 reg-names = "nand_data", "denali_reg";
351 clock-names = "nand", "nand_x", "ecc";
357 compatible = "mmio-sram";
359 #address-cells = <1>;
360 #size-cells = <1>;
364 pdma: dma-controller@ffda0000 {
376 #dma-cells = <1>;
378 clock-names = "apb_pclk";
380 reset-names = "dma", "dma-ocp";
384 compatible = "pinctrl-single";
386 #pinctrl-cells = <1>;
387 pinctrl-single,register-width = <32>;
388 pinctrl-single,function-mask = <0x0000000f>;
392 compatible = "pinctrl-single";
394 #pinctrl-cells = <1>;
395 pinctrl-single,register-width = <32>;
396 pinctrl-single,function-mask = <0x0000000f>;
400 #reset-cells = <1>;
401 compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr";
406 compatible = "arm,mmu-500", "arm,smmu-v2";
408 #global-interrupts = <2>;
409 #iommu-cells = <1>;
411 clock-names = "iommu";
412 interrupt-parent = <&intc>;
414 <0 129 4>, /* Global Non-secure Fault */
415 /* Non-secure Context Interrupts (32) */
424 stream-match-mask = <0x7ff0>;
429 compatible = "snps,dw-apb-ssi";
430 #address-cells = <1>;
431 #size-cells = <0>;
435 reset-names = "spi";
436 reg-io-width = <4>;
437 num-cs = <4>;
443 compatible = "snps,dw-apb-ssi";
444 #address-cells = <1>;
445 #size-cells = <0>;
449 reset-names = "spi";
450 reg-io-width = <4>;
451 num-cs = <4>;
456 sysmgr: sysmgr@ffd12000 { label
457 compatible = "altr,sys-mgr-s10","altr,sys-mgr";
462 compatible = "snps,dw-apb-timer";
466 clock-names = "timer";
470 compatible = "snps,dw-apb-timer";
474 clock-names = "timer";
478 compatible = "snps,dw-apb-timer";
482 clock-names = "timer";
486 compatible = "snps,dw-apb-timer";
490 clock-names = "timer";
494 compatible = "snps,dw-apb-uart";
497 reg-shift = <2>;
498 reg-io-width = <4>;
505 compatible = "snps,dw-apb-uart";
508 reg-shift = <2>;
509 reg-io-width = <4>;
520 phy-names = "usb2-phy";
522 reset-names = "dwc2", "dwc2-ecc";
524 clock-names = "otg";
534 phy-names = "usb2-phy";
536 reset-names = "dwc2", "dwc2-ecc";
538 clock-names = "otg";
544 compatible = "snps,dw-wdt";
553 compatible = "snps,dw-wdt";
562 compatible = "snps,dw-wdt";
571 compatible = "snps,dw-wdt";
580 compatible = "altr,sdr-ctl", "syscon";
585 compatible = "altr,socfpga-s10-ecc-manager",
586 "altr,socfpga-a10-ecc-manager";
587 altr,sysmgr-syscon = <&sysmgr>;
588 #address-cells = <1>;
589 #size-cells = <1>;
591 interrupt-controller;
592 #interrupt-cells = <2>;
596 compatible = "altr,sdram-edac-s10";
597 altr,sdr-syscon = <&sdr>;
601 ocram-ecc@ff8cc000 {
602 compatible = "altr,socfpga-s10-ocram-ecc",
603 "altr,socfpga-a10-ocram-ecc";
605 altr,ecc-parent = <&ocram>;
609 usb0-ecc@ff8c4000 {
610 compatible = "altr,socfpga-s10-usb-ecc",
611 "altr,socfpga-usb-ecc";
613 altr,ecc-parent = <&usb0>;
617 emac0-rx-ecc@ff8c0000 {
618 compatible = "altr,socfpga-s10-eth-mac-ecc",
619 "altr,socfpga-eth-mac-ecc";
621 altr,ecc-parent = <&gmac0>;
625 emac0-tx-ecc@ff8c0400 {
626 compatible = "altr,socfpga-s10-eth-mac-ecc",
627 "altr,socfpga-eth-mac-ecc";
629 altr,ecc-parent = <&gmac0>;
636 compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
637 #address-cells = <1>;
638 #size-cells = <0>;
642 cdns,fifo-depth = <128>;
643 cdns,fifo-width = <4>;
644 cdns,trigger-address = <0x00000000>;
652 compatible = "usb-nop-xceiv";
653 #phy-cells = <0>;