Lines Matching +full:rst +full:- +full:mgr
1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
18 #size-cells = <2>;
22 compatible = "shared-dma-pool";
25 no-map;
30 #address-cells = <1>;
31 #size-cells = <0>;
34 compatible = "arm,cortex-a53";
36 enable-method = "psci";
37 next-level-cache = <&l2_shared>;
42 compatible = "arm,cortex-a53";
44 enable-method = "psci";
45 next-level-cache = <&l2_shared>;
50 compatible = "arm,cortex-a53";
52 enable-method = "psci";
53 next-level-cache = <&l2_shared>;
58 compatible = "arm,cortex-a53";
60 enable-method = "psci";
61 next-level-cache = <&l2_shared>;
67 cache-level = <2>;
68 cache-unified;
74 compatible = "intel,stratix10-svc";
76 memory-region = <&service_reserved>;
78 fpga_mgr: fpga-mgr {
79 compatible = "intel,stratix10-soc-fpga-mgr";
84 fpga-region {
85 compatible = "fpga-region";
86 #address-cells = <0x2>;
87 #size-cells = <0x2>;
88 fpga-mgr = <&fpga_mgr>;
92 compatible = "arm,cortex-a53-pmu";
97 interrupt-affinity = <&cpu0>,
101 interrupt-parent = <&intc>;
105 compatible = "arm,psci-0.2";
111 compatible = "arm,armv8-timer";
116 interrupt-parent = <&intc>;
119 intc: interrupt-controller@fffc1000 {
120 compatible = "arm,gic-400", "arm,cortex-a15-gic";
121 #interrupt-cells = <3>;
122 interrupt-controller;
130 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
131 #clock-cells = <0>;
132 compatible = "fixed-clock";
135 cb_intosc_ls_clk: cb-intosc-ls-clk {
136 #clock-cells = <0>;
137 compatible = "fixed-clock";
140 f2s_free_clk: f2s-free-clk {
141 #clock-cells = <0>;
142 compatible = "fixed-clock";
146 #clock-cells = <0>;
147 compatible = "fixed-clock";
150 qspi_clk: qspi-clk {
151 #clock-cells = <0>;
152 compatible = "fixed-clock";
153 clock-frequency = <200000000>;
158 #address-cells = <1>;
159 #size-cells = <1>;
160 compatible = "simple-bus";
162 interrupt-parent = <&intc>;
165 clkmgr: clock-controller@ffd10000 {
166 compatible = "intel,stratix10-clkmgr";
168 #clock-cells = <1>;
172 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
175 interrupt-names = "macirq";
176 mac-address = [00 00 00 00 00 00];
177 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
178 reset-names = "stmmaceth", "ahb";
180 clock-names = "stmmaceth", "ptp_ref";
181 tx-fifo-depth = <16384>;
182 rx-fifo-depth = <16384>;
183 snps,multicast-filter-bins = <256>;
185 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
190 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
193 interrupt-names = "macirq";
194 mac-address = [00 00 00 00 00 00];
195 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
196 reset-names = "stmmaceth", "ahb";
198 clock-names = "stmmaceth", "ptp_ref";
199 tx-fifo-depth = <16384>;
200 rx-fifo-depth = <16384>;
201 snps,multicast-filter-bins = <256>;
203 altr,sysmgr-syscon = <&sysmgr 0x48 8>;
208 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
211 interrupt-names = "macirq";
212 mac-address = [00 00 00 00 00 00];
213 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
214 reset-names = "stmmaceth", "ahb";
216 clock-names = "stmmaceth", "ptp_ref";
217 tx-fifo-depth = <16384>;
218 rx-fifo-depth = <16384>;
219 snps,multicast-filter-bins = <256>;
221 altr,sysmgr-syscon = <&sysmgr 0x4c 16>;
226 #address-cells = <1>;
227 #size-cells = <0>;
228 compatible = "snps,dw-apb-gpio";
230 resets = <&rst GPIO0_RESET>;
233 porta: gpio-controller@0 {
234 compatible = "snps,dw-apb-gpio-port";
235 gpio-controller;
236 #gpio-cells = <2>;
239 interrupt-controller;
240 #interrupt-cells = <2>;
246 #address-cells = <1>;
247 #size-cells = <0>;
248 compatible = "snps,dw-apb-gpio";
250 resets = <&rst GPIO1_RESET>;
253 portb: gpio-controller@0 {
254 compatible = "snps,dw-apb-gpio-port";
255 gpio-controller;
256 #gpio-cells = <2>;
259 interrupt-controller;
260 #interrupt-cells = <2>;
266 #address-cells = <1>;
267 #size-cells = <0>;
268 compatible = "snps,designware-i2c";
271 resets = <&rst I2C0_RESET>;
277 #address-cells = <1>;
278 #size-cells = <0>;
279 compatible = "snps,designware-i2c";
282 resets = <&rst I2C1_RESET>;
288 #address-cells = <1>;
289 #size-cells = <0>;
290 compatible = "snps,designware-i2c";
293 resets = <&rst I2C2_RESET>;
299 #address-cells = <1>;
300 #size-cells = <0>;
301 compatible = "snps,designware-i2c";
304 resets = <&rst I2C3_RESET>;
310 #address-cells = <1>;
311 #size-cells = <0>;
312 compatible = "snps,designware-i2c";
315 resets = <&rst I2C4_RESET>;
321 #address-cells = <1>;
322 #size-cells = <0>;
323 compatible = "altr,socfpga-dw-mshc";
326 fifo-depth = <0x400>;
327 resets = <&rst SDMMC_RESET>;
328 reset-names = "reset";
331 clock-names = "biu", "ciu";
333 altr,sysmgr-syscon = <&sysmgr 0x28 4>;
337 nand: nand-controller@ffb90000 {
338 #address-cells = <1>;
339 #size-cells = <0>;
340 compatible = "altr,socfpga-denali-nand";
343 reg-names = "nand_data", "denali_reg";
348 clock-names = "nand", "nand_x", "ecc";
349 resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>;
354 compatible = "mmio-sram";
356 #address-cells = <1>;
357 #size-cells = <1>;
361 pdma: dma-controller@ffda0000 {
373 #dma-cells = <1>;
375 clock-names = "apb_pclk";
376 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
377 reset-names = "dma", "dma-ocp";
381 compatible = "pinctrl-single";
383 #pinctrl-cells = <1>;
384 pinctrl-single,register-width = <32>;
385 pinctrl-single,function-mask = <0x0000000f>;
389 compatible = "pinctrl-single";
391 #pinctrl-cells = <1>;
392 pinctrl-single,register-width = <32>;
393 pinctrl-single,function-mask = <0x0000000f>;
396 rst: rstmgr@ffd11000 { label
397 #reset-cells = <1>;
398 compatible = "altr,stratix10-rst-mgr";
403 compatible = "arm,mmu-500", "arm,smmu-v2";
405 #global-interrupts = <2>;
406 #iommu-cells = <1>;
408 clock-names = "iommu";
409 interrupt-parent = <&intc>;
411 <0 129 4>, /* Global Non-secure Fault */
412 /* Non-secure Context Interrupts (32) */
421 stream-match-mask = <0x7ff0>;
426 compatible = "snps,dw-apb-ssi";
427 #address-cells = <1>;
428 #size-cells = <0>;
431 resets = <&rst SPIM0_RESET>;
432 reset-names = "spi";
433 reg-io-width = <4>;
434 num-cs = <4>;
440 compatible = "snps,dw-apb-ssi";
441 #address-cells = <1>;
442 #size-cells = <0>;
445 resets = <&rst SPIM1_RESET>;
446 reset-names = "spi";
447 reg-io-width = <4>;
448 num-cs = <4>;
454 compatible = "altr,sys-mgr-s10","altr,sys-mgr";
459 compatible = "snps,dw-apb-timer";
463 clock-names = "timer";
467 compatible = "snps,dw-apb-timer";
471 clock-names = "timer";
475 compatible = "snps,dw-apb-timer";
479 clock-names = "timer";
483 compatible = "snps,dw-apb-timer";
487 clock-names = "timer";
491 compatible = "snps,dw-apb-uart";
494 reg-shift = <2>;
495 reg-io-width = <4>;
496 resets = <&rst UART0_RESET>;
502 compatible = "snps,dw-apb-uart";
505 reg-shift = <2>;
506 reg-io-width = <4>;
507 resets = <&rst UART1_RESET>;
517 phy-names = "usb2-phy";
518 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
519 reset-names = "dwc2", "dwc2-ecc";
521 clock-names = "otg";
531 phy-names = "usb2-phy";
532 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
533 reset-names = "dwc2", "dwc2-ecc";
535 clock-names = "otg";
541 compatible = "snps,dw-wdt";
544 resets = <&rst WATCHDOG0_RESET>;
550 compatible = "snps,dw-wdt";
553 resets = <&rst WATCHDOG1_RESET>;
559 compatible = "snps,dw-wdt";
562 resets = <&rst WATCHDOG2_RESET>;
568 compatible = "snps,dw-wdt";
571 resets = <&rst WATCHDOG3_RESET>;
577 compatible = "altr,sdr-ctl", "syscon";
582 compatible = "altr,socfpga-s10-ecc-manager",
583 "altr,socfpga-a10-ecc-manager";
584 altr,sysmgr-syscon = <&sysmgr>;
585 #address-cells = <1>;
586 #size-cells = <1>;
588 interrupt-controller;
589 #interrupt-cells = <2>;
593 compatible = "altr,sdram-edac-s10";
594 altr,sdr-syscon = <&sdr>;
598 ocram-ecc@ff8cc000 {
599 compatible = "altr,socfpga-s10-ocram-ecc",
600 "altr,socfpga-a10-ocram-ecc";
602 altr,ecc-parent = <&ocram>;
606 usb0-ecc@ff8c4000 {
607 compatible = "altr,socfpga-s10-usb-ecc",
608 "altr,socfpga-usb-ecc";
610 altr,ecc-parent = <&usb0>;
614 emac0-rx-ecc@ff8c0000 {
615 compatible = "altr,socfpga-s10-eth-mac-ecc",
616 "altr,socfpga-eth-mac-ecc";
618 altr,ecc-parent = <&gmac0>;
622 emac0-tx-ecc@ff8c0400 {
623 compatible = "altr,socfpga-s10-eth-mac-ecc",
624 "altr,socfpga-eth-mac-ecc";
626 altr,ecc-parent = <&gmac0>;
633 compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
634 #address-cells = <1>;
635 #size-cells = <0>;
639 cdns,fifo-depth = <128>;
640 cdns,fifo-width = <4>;
641 cdns,trigger-address = <0x00000000>;
649 compatible = "usb-nop-xceiv";
650 #phy-cells = <0>;