Lines Matching +full:usb +full:- +full:uart +full:- +full:rx
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/sun50i-h616-ccu.h>
8 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
9 #include <dt-bindings/clock/sun6i-rtc.h>
10 #include <dt-bindings/reset/sun50i-h616-ccu.h>
11 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
12 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
24 compatible = "arm,cortex-a53";
27 enable-method = "psci";
29 #cooling-cells = <2>;
30 i-cache-size = <0x8000>;
31 i-cache-line-size = <64>;
32 i-cache-sets = <256>;
33 d-cache-size = <0x8000>;
34 d-cache-line-size = <64>;
35 d-cache-sets = <128>;
36 next-level-cache = <&l2_cache>;
40 compatible = "arm,cortex-a53";
43 enable-method = "psci";
45 #cooling-cells = <2>;
46 i-cache-size = <0x8000>;
47 i-cache-line-size = <64>;
48 i-cache-sets = <256>;
49 d-cache-size = <0x8000>;
50 d-cache-line-size = <64>;
51 d-cache-sets = <128>;
52 next-level-cache = <&l2_cache>;
56 compatible = "arm,cortex-a53";
59 enable-method = "psci";
61 #cooling-cells = <2>;
62 i-cache-size = <0x8000>;
63 i-cache-line-size = <64>;
64 i-cache-sets = <256>;
65 d-cache-size = <0x8000>;
66 d-cache-line-size = <64>;
67 d-cache-sets = <128>;
68 next-level-cache = <&l2_cache>;
72 compatible = "arm,cortex-a53";
75 enable-method = "psci";
77 #cooling-cells = <2>;
78 i-cache-size = <0x8000>;
79 i-cache-line-size = <64>;
80 i-cache-sets = <256>;
81 d-cache-size = <0x8000>;
82 d-cache-line-size = <64>;
83 d-cache-sets = <128>;
84 next-level-cache = <&l2_cache>;
87 l2_cache: l2-cache {
89 cache-level = <2>;
90 cache-unified;
91 cache-size = <0x40000>;
92 cache-line-size = <64>;
93 cache-sets = <256>;
97 reserved-memory {
98 #address-cells = <2>;
99 #size-cells = <2>;
103 * 256 KiB reserved for Trusted Firmware-A (BL31).
109 no-map;
113 osc24M: osc24M-clk {
114 #clock-cells = <0>;
115 compatible = "fixed-clock";
116 clock-frequency = <24000000>;
117 clock-output-names = "osc24M";
121 compatible = "arm,cortex-a53-pmu";
126 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
130 compatible = "arm,psci-0.2";
135 compatible = "arm,armv8-timer";
136 arm,no-tick-in-suspend;
148 compatible = "simple-bus";
149 #address-cells = <1>;
150 #size-cells = <1>;
154 compatible = "allwinner,sun50i-h616-crypto";
159 clock-names = "bus", "mod", "ram", "trng";
164 compatible = "allwinner,sun50i-h616-system-control";
166 #address-cells = <1>;
167 #size-cells = <1>;
171 compatible = "mmio-sram";
173 #address-cells = <1>;
174 #size-cells = <1>;
180 compatible = "allwinner,sun50i-h616-ccu";
183 clock-names = "hosc", "losc", "iosc";
184 #clock-cells = <1>;
185 #reset-cells = <1>;
188 dma: dma-controller@3002000 {
189 compatible = "allwinner,sun50i-h616-dma",
190 "allwinner,sun50i-a100-dma";
194 clock-names = "bus", "mbus";
195 dma-channels = <16>;
196 dma-requests = <49>;
198 #dma-cells = <1>;
202 compatible = "allwinner,sun50i-h616-sid", "allwinner,sun50i-a64-sid";
204 #address-cells = <1>;
205 #size-cells = <1>;
207 ths_calibration: thermal-sensor-calibration@14 {
211 cpu_speed_grade: cpu-speed-grade@0 {
217 compatible = "allwinner,sun50i-h616-wdt",
218 "allwinner,sun6i-a31-wdt";
225 compatible = "allwinner,sun50i-h616-pinctrl";
236 clock-names = "apb", "hosc", "losc";
237 gpio-controller;
238 #gpio-cells = <3>;
239 interrupt-controller;
240 #interrupt-cells = <3>;
242 ext_rgmii_pins: rgmii-pins {
248 drive-strength = <40>;
251 i2c0_pins: i2c0-pins {
256 i2c3_ph_pins: i2c3-ph-pins {
261 ir_rx_pin: ir-rx-pin {
266 mmc0_pins: mmc0-pins {
270 drive-strength = <30>;
271 bias-pull-up;
274 /omit-if-no-ref/
275 mmc1_pins: mmc1-pins {
279 drive-strength = <30>;
280 bias-pull-up;
283 mmc2_pins: mmc2-pins {
288 drive-strength = <30>;
289 bias-pull-up;
292 /omit-if-no-ref/
293 spi0_pins: spi0-pins {
298 /omit-if-no-ref/
299 spi0_cs0_pin: spi0-cs0-pin {
304 /omit-if-no-ref/
305 spi1_pins: spi1-pins {
310 /omit-if-no-ref/
311 spi1_cs0_pin: spi1-cs0-pin {
316 spdif_tx_pin: spdif-tx-pin {
321 uart0_ph_pins: uart0-ph-pins {
326 /omit-if-no-ref/
327 uart1_pins: uart1-pins {
332 /omit-if-no-ref/
333 uart1_rts_cts_pins: uart1-rts-cts-pins {
338 /omit-if-no-ref/
339 x32clk_fanout_pin: x32clk-fanout-pin {
345 gic: interrupt-controller@3021000 {
346 compatible = "arm,gic-400";
352 interrupt-controller;
353 #interrupt-cells = <3>;
357 compatible = "allwinner,sun50i-h616-iommu";
362 #iommu-cells = <1>;
366 compatible = "allwinner,sun50i-h616-mmc",
367 "allwinner,sun50i-a100-mmc";
370 clock-names = "ahb", "mmc";
372 reset-names = "ahb";
374 pinctrl-names = "default";
375 pinctrl-0 = <&mmc0_pins>;
377 max-frequency = <150000000>;
378 cap-sd-highspeed;
379 cap-mmc-highspeed;
380 mmc-ddr-3_3v;
381 cap-sdio-irq;
382 #address-cells = <1>;
383 #size-cells = <0>;
387 compatible = "allwinner,sun50i-h616-mmc",
388 "allwinner,sun50i-a100-mmc";
391 clock-names = "ahb", "mmc";
393 reset-names = "ahb";
395 pinctrl-names = "default";
396 pinctrl-0 = <&mmc1_pins>;
398 max-frequency = <150000000>;
399 cap-sd-highspeed;
400 cap-mmc-highspeed;
401 mmc-ddr-3_3v;
402 cap-sdio-irq;
403 #address-cells = <1>;
404 #size-cells = <0>;
408 compatible = "allwinner,sun50i-h616-emmc",
409 "allwinner,sun50i-a100-emmc";
412 clock-names = "ahb", "mmc";
414 reset-names = "ahb";
416 pinctrl-names = "default";
417 pinctrl-0 = <&mmc2_pins>;
419 max-frequency = <150000000>;
420 cap-sd-highspeed;
421 cap-mmc-highspeed;
422 mmc-ddr-3_3v;
423 cap-sdio-irq;
424 #address-cells = <1>;
425 #size-cells = <0>;
429 compatible = "snps,dw-apb-uart";
432 reg-shift = <2>;
433 reg-io-width = <4>;
436 dma-names = "tx", "rx";
442 compatible = "snps,dw-apb-uart";
445 reg-shift = <2>;
446 reg-io-width = <4>;
449 dma-names = "tx", "rx";
455 compatible = "snps,dw-apb-uart";
458 reg-shift = <2>;
459 reg-io-width = <4>;
462 dma-names = "tx", "rx";
468 compatible = "snps,dw-apb-uart";
471 reg-shift = <2>;
472 reg-io-width = <4>;
475 dma-names = "tx", "rx";
481 compatible = "snps,dw-apb-uart";
484 reg-shift = <2>;
485 reg-io-width = <4>;
488 dma-names = "tx", "rx";
494 compatible = "snps,dw-apb-uart";
497 reg-shift = <2>;
498 reg-io-width = <4>;
501 dma-names = "tx", "rx";
507 compatible = "allwinner,sun50i-h616-i2c",
508 "allwinner,sun8i-v536-i2c",
509 "allwinner,sun6i-a31-i2c";
514 dma-names = "rx", "tx";
516 pinctrl-names = "default";
517 pinctrl-0 = <&i2c0_pins>;
519 #address-cells = <1>;
520 #size-cells = <0>;
524 compatible = "allwinner,sun50i-h616-i2c",
525 "allwinner,sun8i-v536-i2c",
526 "allwinner,sun6i-a31-i2c";
531 dma-names = "rx", "tx";
534 #address-cells = <1>;
535 #size-cells = <0>;
539 compatible = "allwinner,sun50i-h616-i2c",
540 "allwinner,sun8i-v536-i2c",
541 "allwinner,sun6i-a31-i2c";
546 dma-names = "rx", "tx";
549 #address-cells = <1>;
550 #size-cells = <0>;
554 compatible = "allwinner,sun50i-h616-i2c",
555 "allwinner,sun8i-v536-i2c",
556 "allwinner,sun6i-a31-i2c";
561 dma-names = "rx", "tx";
564 #address-cells = <1>;
565 #size-cells = <0>;
569 compatible = "allwinner,sun50i-h616-i2c",
570 "allwinner,sun8i-v536-i2c",
571 "allwinner,sun6i-a31-i2c";
576 dma-names = "rx", "tx";
579 #address-cells = <1>;
580 #size-cells = <0>;
584 compatible = "allwinner,sun50i-h616-spi",
585 "allwinner,sun8i-h3-spi";
589 clock-names = "ahb", "mod";
591 dma-names = "rx", "tx";
594 #address-cells = <1>;
595 #size-cells = <0>;
599 compatible = "allwinner,sun50i-h616-spi",
600 "allwinner,sun8i-h3-spi";
604 clock-names = "ahb", "mod";
606 dma-names = "rx", "tx";
609 #address-cells = <1>;
610 #size-cells = <0>;
614 compatible = "allwinner,sun50i-h616-emac0",
615 "allwinner,sun50i-a64-emac";
618 interrupt-names = "macirq";
620 clock-names = "stmmaceth";
622 reset-names = "stmmaceth";
627 compatible = "snps,dwmac-mdio";
628 #address-cells = <1>;
629 #size-cells = <0>;
634 compatible = "allwinner,sun50i-h616-gpadc",
635 "allwinner,sun20i-d1-gpadc";
641 #io-channel-cells = <1>;
644 ths: thermal-sensor@5070400 {
645 compatible = "allwinner,sun50i-h616-ths";
649 clock-names = "bus";
651 nvmem-cells = <&ths_calibration>;
652 nvmem-cell-names = "calibration";
654 #thermal-sensor-cells = <1>;
658 compatible = "allwinner,sun50i-h616-lradc",
659 "allwinner,sun50i-r329-lradc";
668 compatible = "allwinner,sun50i-h616-spdif";
672 clock-names = "apb", "spdif";
675 dma-names = "tx";
676 pinctrl-names = "default";
677 pinctrl-0 = <&spdif_tx_pin>;
678 #sound-dai-cells = <0>;
683 #sound-dai-cells = <0>;
684 compatible = "allwinner,sun50i-h616-codec";
689 clock-names = "apb", "codec";
692 dma-names = "tx";
696 usbotg: usb@5100000 {
697 compatible = "allwinner,sun50i-h616-musb",
698 "allwinner,sun8i-h3-musb";
703 interrupt-names = "mc";
705 phy-names = "usb";
711 compatible = "allwinner,sun50i-h616-usb-phy";
717 reg-names = "phy_ctrl",
727 clock-names = "usb0_phy",
736 reset-names = "usb0_reset",
741 #phy-cells = <1>;
744 ehci0: usb@5101000 {
745 compatible = "allwinner,sun50i-h616-ehci",
746 "generic-ehci";
755 phy-names = "usb";
759 ohci0: usb@5101400 {
760 compatible = "allwinner,sun50i-h616-ohci",
761 "generic-ohci";
768 phy-names = "usb";
772 ehci1: usb@5200000 {
773 compatible = "allwinner,sun50i-h616-ehci",
774 "generic-ehci";
783 phy-names = "usb";
787 ohci1: usb@5200400 {
788 compatible = "allwinner,sun50i-h616-ohci",
789 "generic-ohci";
796 phy-names = "usb";
800 ehci2: usb@5310000 {
801 compatible = "allwinner,sun50i-h616-ehci",
802 "generic-ehci";
811 phy-names = "usb";
815 ohci2: usb@5310400 {
816 compatible = "allwinner,sun50i-h616-ohci",
817 "generic-ohci";
824 phy-names = "usb";
828 ehci3: usb@5311000 {
829 compatible = "allwinner,sun50i-h616-ehci",
830 "generic-ehci";
839 phy-names = "usb";
843 ohci3: usb@5311400 {
844 compatible = "allwinner,sun50i-h616-ohci",
845 "generic-ohci";
852 phy-names = "usb";
857 compatible = "allwinner,sun50i-h616-rtc";
862 clock-names = "bus", "hosc",
863 "pll-32k";
864 #clock-cells = <1>;
868 compatible = "allwinner,sun50i-h616-r-ccu";
872 clock-names = "hosc", "losc", "iosc", "pll-periph";
873 #clock-cells = <1>;
874 #reset-cells = <1>;
877 nmi_intc: interrupt-controller@7010320 {
878 compatible = "allwinner,sun50i-h616-nmi",
879 "allwinner,sun9i-a80-nmi";
881 interrupt-controller;
882 #interrupt-cells = <2>;
887 compatible = "allwinner,sun50i-h616-r-pinctrl";
891 clock-names = "apb", "hosc", "losc";
892 gpio-controller;
893 #gpio-cells = <3>;
895 /omit-if-no-ref/
896 r_i2c_pins: r-i2c-pins {
901 r_rsb_pins: r-rsb-pins {
908 compatible = "allwinner,sun50i-h616-ir",
909 "allwinner,sun6i-a31-ir";
914 clock-names = "apb", "ir";
916 pinctrl-names = "default";
917 pinctrl-0 = <&ir_rx_pin>;
922 compatible = "allwinner,sun50i-h616-i2c",
923 "allwinner,sun8i-v536-i2c",
924 "allwinner,sun6i-a31-i2c";
929 dma-names = "rx", "tx";
931 pinctrl-names = "default";
932 pinctrl-0 = <&r_i2c_pins>;
934 #address-cells = <1>;
935 #size-cells = <0>;
939 compatible = "allwinner,sun50i-h616-rsb",
940 "allwinner,sun8i-a23-rsb";
944 clock-frequency = <3000000>;
946 pinctrl-names = "default";
947 pinctrl-0 = <&r_rsb_pins>;
949 #address-cells = <1>;
950 #size-cells = <0>;
954 thermal-zones {
955 cpu-thermal {
956 polling-delay-passive = <500>;
957 polling-delay = <1000>;
958 thermal-sensors = <&ths 2>;
959 sustainable-power = <1000>;
962 cpu_threshold: cpu-trip-0 {
967 cpu_target: cpu-trip-1 {
972 cpu_critical: cpu-trip-2 {
980 gpu-thermal {
981 polling-delay-passive = <500>;
982 polling-delay = <1000>;
983 thermal-sensors = <&ths 0>;
984 sustainable-power = <1100>;
987 gpu_temp_critical: gpu-trip-0 {
995 ve-thermal {
996 polling-delay-passive = <0>;
997 polling-delay = <0>;
998 thermal-sensors = <&ths 1>;
1001 ve_temp_critical: ve-trip-0 {
1009 ddr-thermal {
1010 polling-delay-passive = <0>;
1011 polling-delay = <0>;
1012 thermal-sensors = <&ths 3>;
1015 ddr_temp_critical: ddr-trip-0 {