Lines Matching +full:sun4i +full:- +full:a10 +full:- +full:ir
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/sun50i-a64-ccu.h>
7 #include <dt-bindings/clock/sun6i-rtc.h>
8 #include <dt-bindings/clock/sun8i-de2.h>
9 #include <dt-bindings/clock/sun8i-r-ccu.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/sun50i-a64-ccu.h>
12 #include <dt-bindings/reset/sun8i-de2.h>
13 #include <dt-bindings/reset/sun8i-r-ccu.h>
14 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <1>;
19 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <1>;
26 simplefb_lcd: framebuffer-lcd {
27 compatible = "allwinner,simple-framebuffer",
28 "simple-framebuffer";
29 allwinner,pipeline = "mixer0-lcd0";
35 simplefb_hdmi: framebuffer-hdmi {
36 compatible = "allwinner,simple-framebuffer",
37 "simple-framebuffer";
38 allwinner,pipeline = "mixer1-lcd1-hdmi";
46 #address-cells = <1>;
47 #size-cells = <0>;
50 compatible = "arm,cortex-a53";
53 enable-method = "psci";
55 clock-names = "cpu";
56 #cooling-cells = <2>;
57 i-cache-size = <0x8000>;
58 i-cache-line-size = <64>;
59 i-cache-sets = <256>;
60 d-cache-size = <0x8000>;
61 d-cache-line-size = <64>;
62 d-cache-sets = <128>;
63 next-level-cache = <&l2_cache>;
67 compatible = "arm,cortex-a53";
70 enable-method = "psci";
72 clock-names = "cpu";
73 #cooling-cells = <2>;
74 i-cache-size = <0x8000>;
75 i-cache-line-size = <64>;
76 i-cache-sets = <256>;
77 d-cache-size = <0x8000>;
78 d-cache-line-size = <64>;
79 d-cache-sets = <128>;
80 next-level-cache = <&l2_cache>;
84 compatible = "arm,cortex-a53";
87 enable-method = "psci";
89 clock-names = "cpu";
90 #cooling-cells = <2>;
91 i-cache-size = <0x8000>;
92 i-cache-line-size = <64>;
93 i-cache-sets = <256>;
94 d-cache-size = <0x8000>;
95 d-cache-line-size = <64>;
96 d-cache-sets = <128>;
97 next-level-cache = <&l2_cache>;
101 compatible = "arm,cortex-a53";
104 enable-method = "psci";
106 clock-names = "cpu";
107 #cooling-cells = <2>;
108 i-cache-size = <0x8000>;
109 i-cache-line-size = <64>;
110 i-cache-sets = <256>;
111 d-cache-size = <0x8000>;
112 d-cache-line-size = <64>;
113 d-cache-sets = <128>;
114 next-level-cache = <&l2_cache>;
117 l2_cache: l2-cache {
119 cache-level = <2>;
120 cache-unified;
121 cache-size = <0x80000>;
122 cache-line-size = <64>;
123 cache-sets = <512>;
127 de: display-engine {
128 compatible = "allwinner,sun50i-a64-display-engine";
134 gpu_opp_table: opp-table-gpu {
135 compatible = "operating-points-v2";
137 opp-432000000 {
138 opp-hz = /bits/ 64 <432000000>;
142 osc24M: osc24M-clk {
143 #clock-cells = <0>;
144 compatible = "fixed-clock";
145 clock-frequency = <24000000>;
146 clock-output-names = "osc24M";
149 osc32k: osc32k-clk {
150 #clock-cells = <0>;
151 compatible = "fixed-clock";
152 clock-frequency = <32768>;
153 clock-output-names = "ext-osc32k";
157 compatible = "arm,cortex-a53-pmu";
162 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
166 compatible = "arm,psci-0.2";
171 #address-cells = <1>;
172 #size-cells = <0>;
173 compatible = "simple-audio-card";
174 simple-audio-card,name = "sun50i-a64-audio";
175 simple-audio-card,aux-devs = <&codec_analog>;
176 simple-audio-card,routing =
183 simple-audio-card,dai-link@0 {
185 frame-master = <&link0_cpu>;
186 bitclock-master = <&link0_cpu>;
187 mclk-fs = <128>;
190 sound-dai = <&dai>;
194 sound-dai = <&codec 0>;
200 compatible = "arm,armv8-timer";
201 allwinner,erratum-unknown1;
202 arm,no-tick-in-suspend;
213 thermal-zones {
214 cpu_thermal: cpu0-thermal {
216 polling-delay-passive = <0>;
217 polling-delay = <0>;
218 thermal-sensors = <&ths 0>;
220 cooling-maps {
223 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
230 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
238 cpu_alert0: cpu-alert0 {
245 cpu_alert1: cpu-alert1 {
252 cpu_crit: cpu-crit {
261 gpu0_thermal: gpu0-thermal {
263 polling-delay-passive = <0>;
264 polling-delay = <0>;
265 thermal-sensors = <&ths 1>;
268 gpu0_crit: gpu0-crit {
276 gpu1_thermal: gpu1-thermal {
278 polling-delay-passive = <0>;
279 polling-delay = <0>;
280 thermal-sensors = <&ths 2>;
283 gpu1_crit: gpu1-crit {
293 compatible = "simple-bus";
294 #address-cells = <1>;
295 #size-cells = <1>;
299 compatible = "allwinner,sun50i-a64-de2";
302 #address-cells = <1>;
303 #size-cells = <1>;
307 compatible = "allwinner,sun50i-a64-de2-clk";
311 clock-names = "bus",
314 #clock-cells = <1>;
315 #reset-cells = <1>;
319 compatible = "allwinner,sun50i-a64-de2-rotate",
320 "allwinner,sun8i-a83t-de2-rotate";
325 clock-names = "bus",
331 compatible = "allwinner,sun50i-a64-de2-mixer-0";
335 clock-names = "bus",
340 #address-cells = <1>;
341 #size-cells = <0>;
344 #address-cells = <1>;
345 #size-cells = <0>;
350 remote-endpoint = <&tcon0_in_mixer0>;
355 remote-endpoint = <&tcon1_in_mixer0>;
362 compatible = "allwinner,sun50i-a64-de2-mixer-1";
366 clock-names = "bus",
371 #address-cells = <1>;
372 #size-cells = <0>;
375 #address-cells = <1>;
376 #size-cells = <0>;
381 remote-endpoint = <&tcon0_in_mixer1>;
386 remote-endpoint = <&tcon1_in_mixer1>;
394 compatible = "allwinner,sun50i-a64-system-control";
396 #address-cells = <1>;
397 #size-cells = <1>;
401 compatible = "mmio-sram";
403 #address-cells = <1>;
404 #size-cells = <1>;
407 de2_sram: sram-section@0 {
408 compatible = "allwinner,sun50i-a64-sram-c";
414 compatible = "mmio-sram";
416 #address-cells = <1>;
417 #size-cells = <1>;
420 ve_sram: sram-section@0 {
421 compatible = "allwinner,sun50i-a64-sram-c1",
422 "allwinner,sun4i-a10-sram-c1";
428 dma: dma-controller@1c02000 {
429 compatible = "allwinner,sun50i-a64-dma";
433 dma-channels = <8>;
434 dma-requests = <27>;
436 #dma-cells = <1>;
439 tcon0: lcd-controller@1c0c000 {
440 compatible = "allwinner,sun50i-a64-tcon-lcd",
441 "allwinner,sun8i-a83t-tcon-lcd";
445 clock-names = "ahb", "tcon-ch0";
446 clock-output-names = "tcon-data-clock";
447 #clock-cells = <0>;
448 assigned-clocks = <&ccu CLK_TCON0>;
449 assigned-clock-parents = <&ccu CLK_PLL_MIPI>;
451 reset-names = "lcd", "lvds";
454 #address-cells = <1>;
455 #size-cells = <0>;
458 #address-cells = <1>;
459 #size-cells = <0>;
464 remote-endpoint = <&mixer0_out_tcon0>;
469 remote-endpoint = <&mixer1_out_tcon0>;
474 #address-cells = <1>;
475 #size-cells = <0>;
480 remote-endpoint = <&dsi_in_tcon0>;
481 allwinner,tcon-channel = <1>;
487 tcon1: lcd-controller@1c0d000 {
488 compatible = "allwinner,sun50i-a64-tcon-tv",
489 "allwinner,sun8i-a83t-tcon-tv";
493 clock-names = "ahb", "tcon-ch1";
495 reset-names = "lcd";
498 #address-cells = <1>;
499 #size-cells = <0>;
502 #address-cells = <1>;
503 #size-cells = <0>;
508 remote-endpoint = <&mixer0_out_tcon1>;
513 remote-endpoint = <&mixer1_out_tcon1>;
518 #address-cells = <1>;
519 #size-cells = <0>;
524 remote-endpoint = <&hdmi_in_tcon1>;
530 video-codec@1c0e000 {
531 compatible = "allwinner,sun50i-a64-video-engine";
535 clock-names = "ahb", "mod", "ram";
542 compatible = "allwinner,sun50i-a64-mmc";
545 clock-names = "ahb", "mmc";
547 reset-names = "ahb";
549 max-frequency = <150000000>;
551 #address-cells = <1>;
552 #size-cells = <0>;
556 compatible = "allwinner,sun50i-a64-mmc";
559 clock-names = "ahb", "mmc";
561 reset-names = "ahb";
563 max-frequency = <150000000>;
565 #address-cells = <1>;
566 #size-cells = <0>;
570 compatible = "allwinner,sun50i-a64-emmc";
573 clock-names = "ahb", "mmc";
575 reset-names = "ahb";
577 max-frequency = <150000000>;
579 #address-cells = <1>;
580 #size-cells = <0>;
584 compatible = "allwinner,sun50i-a64-sid";
586 #address-cells = <1>;
587 #size-cells = <1>;
589 ths_calibration: thermal-sensor-calibration@34 {
595 compatible = "allwinner,sun50i-a64-crypto";
599 clock-names = "bus", "mod";
604 compatible = "allwinner,sun50i-a64-msgbox",
605 "allwinner,sun6i-a31-msgbox";
610 #mbox-cells = <1>;
614 compatible = "allwinner,sun8i-a33-musb";
619 interrupt-names = "mc";
621 phy-names = "usb";
628 compatible = "allwinner,sun50i-a64-usb-phy";
632 reg-names = "phy_ctrl",
637 clock-names = "usb0_phy",
641 reset-names = "usb0_reset",
644 #phy-cells = <1>;
648 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
657 phy-names = "usb";
662 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
669 phy-names = "usb";
674 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
683 phy-names = "usb";
688 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
695 phy-names = "usb";
700 compatible = "allwinner,sun50i-a64-ccu";
703 clock-names = "hosc", "losc";
704 #clock-cells = <1>;
705 #reset-cells = <1>;
709 compatible = "allwinner,sun50i-a64-pinctrl";
711 interrupt-parent = <&r_intc>;
717 clock-names = "apb", "hosc", "losc";
718 gpio-controller;
719 #gpio-cells = <3>;
720 interrupt-controller;
721 #interrupt-cells = <3>;
723 /omit-if-no-ref/
724 aif2_pins: aif2-pins {
729 /omit-if-no-ref/
730 aif3_pins: aif3-pins {
735 csi_pins: csi-pins {
741 /omit-if-no-ref/
742 csi_mclk_pin: csi-mclk-pin {
747 i2c0_pins: i2c0-pins {
752 i2c1_pins: i2c1-pins {
757 i2c2_pins: i2c2-pins {
762 /omit-if-no-ref/
763 lcd_rgb666_pins: lcd-rgb666-pins {
772 mmc0_pins: mmc0-pins {
776 drive-strength = <30>;
777 bias-pull-up;
780 mmc1_pins: mmc1-pins {
784 drive-strength = <30>;
785 bias-pull-up;
788 mmc2_pins: mmc2-pins {
793 drive-strength = <30>;
794 bias-pull-up;
797 mmc2_ds_pin: mmc2-ds-pin {
800 drive-strength = <30>;
801 bias-pull-up;
804 pwm_pin: pwm-pin {
809 rmii_pins: rmii-pins {
813 drive-strength = <40>;
816 rgmii_pins: rgmii-pins {
821 drive-strength = <40>;
824 spdif_tx_pin: spdif-tx-pin {
829 spi0_pins: spi0-pins {
834 spi1_pins: spi1-pins {
839 uart0_pb_pins: uart0-pb-pins {
844 uart1_pins: uart1-pins {
849 uart1_rts_cts_pins: uart1-rts-cts-pins {
854 uart2_pins: uart2-pins {
859 uart3_pins: uart3-pins {
864 uart4_pins: uart4-pins {
869 uart4_rts_cts_pins: uart4-rts-cts-pins {
876 compatible = "allwinner,sun50i-a64-timer",
877 "allwinner,sun8i-a23-timer";
885 compatible = "allwinner,sun50i-a64-wdt",
886 "allwinner,sun6i-a31-wdt";
893 #sound-dai-cells = <0>;
894 compatible = "allwinner,sun50i-a64-spdif",
895 "allwinner,sun8i-h3-spdif";
900 clock-names = "apb", "spdif";
902 dma-names = "tx";
903 pinctrl-names = "default";
904 pinctrl-0 = <&spdif_tx_pin>;
909 compatible = "allwinner,sun50i-a64-lradc",
910 "allwinner,sun8i-a83t-r-lradc";
912 interrupt-parent = <&r_intc>;
918 #sound-dai-cells = <0>;
919 compatible = "allwinner,sun50i-a64-i2s",
920 "allwinner,sun8i-h3-i2s";
924 clock-names = "apb", "mod";
926 dma-names = "rx", "tx";
932 #sound-dai-cells = <0>;
933 compatible = "allwinner,sun50i-a64-i2s",
934 "allwinner,sun8i-h3-i2s";
938 clock-names = "apb", "mod";
940 dma-names = "rx", "tx";
946 #sound-dai-cells = <0>;
947 compatible = "allwinner,sun50i-a64-i2s",
948 "allwinner,sun8i-h3-i2s";
952 clock-names = "apb", "mod";
954 dma-names = "rx", "tx";
960 #sound-dai-cells = <0>;
961 compatible = "allwinner,sun50i-a64-codec-i2s";
965 clock-names = "apb", "mod";
968 dma-names = "rx", "tx";
973 #sound-dai-cells = <1>;
974 compatible = "allwinner,sun50i-a64-codec",
975 "allwinner,sun8i-a33-codec";
979 clock-names = "bus", "mod";
983 ths: thermal-sensor@1c25000 {
984 compatible = "allwinner,sun50i-a64-ths";
987 clock-names = "bus", "mod";
990 nvmem-cells = <&ths_calibration>;
991 nvmem-cell-names = "calibration";
992 #thermal-sensor-cells = <1>;
996 compatible = "snps,dw-apb-uart";
999 reg-shift = <2>;
1000 reg-io-width = <4>;
1007 compatible = "snps,dw-apb-uart";
1010 reg-shift = <2>;
1011 reg-io-width = <4>;
1018 compatible = "snps,dw-apb-uart";
1021 reg-shift = <2>;
1022 reg-io-width = <4>;
1029 compatible = "snps,dw-apb-uart";
1032 reg-shift = <2>;
1033 reg-io-width = <4>;
1040 compatible = "snps,dw-apb-uart";
1043 reg-shift = <2>;
1044 reg-io-width = <4>;
1051 compatible = "allwinner,sun6i-a31-i2c";
1056 pinctrl-names = "default";
1057 pinctrl-0 = <&i2c0_pins>;
1059 #address-cells = <1>;
1060 #size-cells = <0>;
1064 compatible = "allwinner,sun6i-a31-i2c";
1069 pinctrl-names = "default";
1070 pinctrl-0 = <&i2c1_pins>;
1072 #address-cells = <1>;
1073 #size-cells = <0>;
1077 compatible = "allwinner,sun6i-a31-i2c";
1082 pinctrl-names = "default";
1083 pinctrl-0 = <&i2c2_pins>;
1085 #address-cells = <1>;
1086 #size-cells = <0>;
1090 compatible = "allwinner,sun8i-h3-spi";
1094 clock-names = "ahb", "mod";
1096 dma-names = "rx", "tx";
1097 pinctrl-names = "default";
1098 pinctrl-0 = <&spi0_pins>;
1101 num-cs = <1>;
1102 #address-cells = <1>;
1103 #size-cells = <0>;
1107 compatible = "allwinner,sun8i-h3-spi";
1111 clock-names = "ahb", "mod";
1113 dma-names = "rx", "tx";
1114 pinctrl-names = "default";
1115 pinctrl-0 = <&spi1_pins>;
1118 num-cs = <1>;
1119 #address-cells = <1>;
1120 #size-cells = <0>;
1124 compatible = "allwinner,sun50i-a64-emac";
1128 interrupt-names = "macirq";
1130 reset-names = "stmmaceth";
1132 clock-names = "stmmaceth";
1136 compatible = "snps,dwmac-mdio";
1137 #address-cells = <1>;
1138 #size-cells = <0>;
1143 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400";
1152 interrupt-names = "gp",
1160 clock-names = "bus", "core";
1162 operating-points-v2 = <&gpu_opp_table>;
1165 gic: interrupt-controller@1c81000 {
1166 compatible = "arm,gic-400";
1172 interrupt-controller;
1173 #interrupt-cells = <3>;
1177 compatible = "allwinner,sun50i-a64-pwm",
1178 "allwinner,sun5i-a13-pwm";
1181 pinctrl-names = "default";
1182 pinctrl-0 = <&pwm_pin>;
1183 #pwm-cells = <3>;
1187 mbus: dram-controller@1c62000 {
1188 compatible = "allwinner,sun50i-a64-mbus";
1191 reg-names = "mbus", "dram";
1195 clock-names = "mbus", "dram", "bus";
1197 #address-cells = <1>;
1198 #size-cells = <1>;
1199 dma-ranges = <0x00000000 0x40000000 0xc0000000>;
1200 #interconnect-cells = <1>;
1204 compatible = "allwinner,sun50i-a64-csi";
1210 clock-names = "bus", "mod", "ram";
1212 pinctrl-names = "default";
1213 pinctrl-0 = <&csi_pins>;
1218 compatible = "allwinner,sun50i-a64-mipi-dsi";
1224 phy-names = "dphy";
1226 #address-cells = <1>;
1227 #size-cells = <0>;
1231 remote-endpoint = <&tcon0_out_dsi>;
1236 dphy: d-phy@1ca1000 {
1237 compatible = "allwinner,sun50i-a64-mipi-dphy",
1238 "allwinner,sun6i-a31-mipi-dphy";
1243 clock-names = "bus", "mod";
1246 #phy-cells = <0>;
1250 compatible = "allwinner,sun50i-a64-deinterlace",
1251 "allwinner,sun8i-h3-deinterlace";
1256 clock-names = "bus", "mod", "ram";
1260 interconnect-names = "dma-mem";
1264 compatible = "allwinner,sun50i-a64-dw-hdmi",
1265 "allwinner,sun8i-a83t-dw-hdmi";
1267 reg-io-width = <1>;
1271 clock-names = "iahb", "isfr", "tmds", "cec";
1273 reset-names = "ctrl";
1275 phy-names = "phy";
1279 #address-cells = <1>;
1280 #size-cells = <0>;
1286 remote-endpoint = <&tcon1_out_hdmi>;
1296 hdmi_phy: hdmi-phy@1ef0000 {
1297 compatible = "allwinner,sun50i-a64-hdmi-phy";
1301 clock-names = "bus", "mod", "pll-0";
1303 reset-names = "phy";
1304 #phy-cells = <0>;
1308 compatible = "allwinner,sun50i-a64-rtc",
1309 "allwinner,sun8i-h3-rtc";
1311 interrupt-parent = <&r_intc>;
1314 clock-output-names = "osc32k", "osc32k-out", "iosc";
1316 #clock-cells = <1>;
1319 r_intc: interrupt-controller@1f00c00 {
1320 compatible = "allwinner,sun50i-a64-r-intc",
1321 "allwinner,sun6i-a31-r-intc";
1322 interrupt-controller;
1323 #interrupt-cells = <3>;
1329 compatible = "allwinner,sun50i-a64-r-ccu";
1333 clock-names = "hosc", "losc", "iosc", "pll-periph";
1334 #clock-cells = <1>;
1335 #reset-cells = <1>;
1338 codec_analog: codec-analog@1f015c0 {
1339 compatible = "allwinner,sun50i-a64-codec-analog";
1345 compatible = "allwinner,sun50i-a64-i2c",
1346 "allwinner,sun6i-a31-i2c";
1352 #address-cells = <1>;
1353 #size-cells = <0>;
1356 r_ir: ir@1f02000 {
1357 compatible = "allwinner,sun50i-a64-ir",
1358 "allwinner,sun6i-a31-ir";
1361 clock-names = "apb", "ir";
1364 pinctrl-names = "default";
1365 pinctrl-0 = <&r_ir_rx_pin>;
1370 compatible = "allwinner,sun50i-a64-pwm",
1371 "allwinner,sun5i-a13-pwm";
1374 pinctrl-names = "default";
1375 pinctrl-0 = <&r_pwm_pin>;
1376 #pwm-cells = <3>;
1381 compatible = "allwinner,sun50i-a64-r-pinctrl";
1383 interrupt-parent = <&r_intc>;
1386 clock-names = "apb", "hosc", "losc";
1387 gpio-controller;
1388 #gpio-cells = <3>;
1389 interrupt-controller;
1390 #interrupt-cells = <3>;
1392 r_i2c_pl89_pins: r-i2c-pl89-pins {
1397 r_ir_rx_pin: r-ir-rx-pin {
1402 r_pwm_pin: r-pwm-pin {
1407 r_rsb_pins: r-rsb-pins {
1414 compatible = "allwinner,sun8i-a23-rsb";
1418 clock-frequency = <3000000>;
1420 pinctrl-names = "default";
1421 pinctrl-0 = <&r_rsb_pins>;
1423 #address-cells = <1>;
1424 #size-cells = <0>;