Lines Matching +full:otg +full:- +full:gp +full:- +full:pins
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/sun50i-a64-ccu.h>
7 #include <dt-bindings/clock/sun6i-rtc.h>
8 #include <dt-bindings/clock/sun8i-de2.h>
9 #include <dt-bindings/clock/sun8i-r-ccu.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/sun50i-a64-ccu.h>
12 #include <dt-bindings/reset/sun8i-de2.h>
13 #include <dt-bindings/reset/sun8i-r-ccu.h>
14 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <1>;
19 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <1>;
26 simplefb_lcd: framebuffer-lcd {
27 compatible = "allwinner,simple-framebuffer",
28 "simple-framebuffer";
29 allwinner,pipeline = "mixer0-lcd0";
35 simplefb_hdmi: framebuffer-hdmi {
36 compatible = "allwinner,simple-framebuffer",
37 "simple-framebuffer";
38 allwinner,pipeline = "mixer1-lcd1-hdmi";
46 #address-cells = <1>;
47 #size-cells = <0>;
50 compatible = "arm,cortex-a53";
53 enable-method = "psci";
55 clock-names = "cpu";
56 #cooling-cells = <2>;
57 i-cache-size = <0x8000>;
58 i-cache-line-size = <64>;
59 i-cache-sets = <256>;
60 d-cache-size = <0x8000>;
61 d-cache-line-size = <64>;
62 d-cache-sets = <128>;
63 next-level-cache = <&l2_cache>;
67 compatible = "arm,cortex-a53";
70 enable-method = "psci";
72 clock-names = "cpu";
73 #cooling-cells = <2>;
74 i-cache-size = <0x8000>;
75 i-cache-line-size = <64>;
76 i-cache-sets = <256>;
77 d-cache-size = <0x8000>;
78 d-cache-line-size = <64>;
79 d-cache-sets = <128>;
80 next-level-cache = <&l2_cache>;
84 compatible = "arm,cortex-a53";
87 enable-method = "psci";
89 clock-names = "cpu";
90 #cooling-cells = <2>;
91 i-cache-size = <0x8000>;
92 i-cache-line-size = <64>;
93 i-cache-sets = <256>;
94 d-cache-size = <0x8000>;
95 d-cache-line-size = <64>;
96 d-cache-sets = <128>;
97 next-level-cache = <&l2_cache>;
101 compatible = "arm,cortex-a53";
104 enable-method = "psci";
106 clock-names = "cpu";
107 #cooling-cells = <2>;
108 i-cache-size = <0x8000>;
109 i-cache-line-size = <64>;
110 i-cache-sets = <256>;
111 d-cache-size = <0x8000>;
112 d-cache-line-size = <64>;
113 d-cache-sets = <128>;
114 next-level-cache = <&l2_cache>;
117 l2_cache: l2-cache {
119 cache-level = <2>;
120 cache-unified;
121 cache-size = <0x80000>;
122 cache-line-size = <64>;
123 cache-sets = <512>;
127 de: display-engine {
128 compatible = "allwinner,sun50i-a64-display-engine";
134 gpu_opp_table: opp-table-gpu {
135 compatible = "operating-points-v2";
137 opp-432000000 {
138 opp-hz = /bits/ 64 <432000000>;
142 osc24M: osc24M-clk {
143 #clock-cells = <0>;
144 compatible = "fixed-clock";
145 clock-frequency = <24000000>;
146 clock-output-names = "osc24M";
149 osc32k: osc32k-clk {
150 #clock-cells = <0>;
151 compatible = "fixed-clock";
152 clock-frequency = <32768>;
153 clock-output-names = "ext-osc32k";
157 compatible = "arm,cortex-a53-pmu";
162 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
166 compatible = "arm,psci-0.2";
171 #address-cells = <1>;
172 #size-cells = <0>;
173 compatible = "simple-audio-card";
174 simple-audio-card,name = "sun50i-a64-audio";
175 simple-audio-card,aux-devs = <&codec_analog>;
176 simple-audio-card,routing =
183 simple-audio-card,dai-link@0 {
185 frame-master = <&link0_cpu>;
186 bitclock-master = <&link0_cpu>;
187 mclk-fs = <128>;
190 sound-dai = <&dai>;
194 sound-dai = <&codec 0>;
200 compatible = "arm,armv8-timer";
201 allwinner,erratum-unknown1;
202 arm,no-tick-in-suspend;
213 thermal-zones {
214 cpu_thermal: cpu0-thermal {
216 polling-delay-passive = <0>;
217 polling-delay = <0>;
218 thermal-sensors = <&ths 0>;
220 cooling-maps {
223 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
230 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
238 cpu_alert0: cpu-alert0 {
245 cpu_alert1: cpu-alert1 {
252 cpu_crit: cpu-crit {
261 gpu0_thermal: gpu0-thermal {
263 polling-delay-passive = <0>;
264 polling-delay = <0>;
265 thermal-sensors = <&ths 1>;
268 gpu0_crit: gpu0-crit {
276 gpu1_thermal: gpu1-thermal {
278 polling-delay-passive = <0>;
279 polling-delay = <0>;
280 thermal-sensors = <&ths 2>;
283 gpu1_crit: gpu1-crit {
293 compatible = "simple-bus";
294 #address-cells = <1>;
295 #size-cells = <1>;
299 compatible = "allwinner,sun50i-a64-de2";
302 #address-cells = <1>;
303 #size-cells = <1>;
307 compatible = "allwinner,sun50i-a64-de2-clk";
311 clock-names = "bus",
314 #clock-cells = <1>;
315 #reset-cells = <1>;
319 compatible = "allwinner,sun50i-a64-de2-rotate",
320 "allwinner,sun8i-a83t-de2-rotate";
325 clock-names = "bus",
331 compatible = "allwinner,sun50i-a64-de2-mixer-0";
335 clock-names = "bus",
340 #address-cells = <1>;
341 #size-cells = <0>;
344 #address-cells = <1>;
345 #size-cells = <0>;
350 remote-endpoint = <&tcon0_in_mixer0>;
355 remote-endpoint = <&tcon1_in_mixer0>;
362 compatible = "allwinner,sun50i-a64-de2-mixer-1";
366 clock-names = "bus",
371 #address-cells = <1>;
372 #size-cells = <0>;
375 #address-cells = <1>;
376 #size-cells = <0>;
381 remote-endpoint = <&tcon0_in_mixer1>;
386 remote-endpoint = <&tcon1_in_mixer1>;
394 compatible = "allwinner,sun50i-a64-system-control";
396 #address-cells = <1>;
397 #size-cells = <1>;
401 compatible = "mmio-sram";
403 #address-cells = <1>;
404 #size-cells = <1>;
407 de2_sram: sram-section@0 {
408 compatible = "allwinner,sun50i-a64-sram-c";
414 compatible = "mmio-sram";
416 #address-cells = <1>;
417 #size-cells = <1>;
420 ve_sram: sram-section@0 {
421 compatible = "allwinner,sun50i-a64-sram-c1",
422 "allwinner,sun4i-a10-sram-c1";
428 dma: dma-controller@1c02000 {
429 compatible = "allwinner,sun50i-a64-dma";
433 dma-channels = <8>;
434 dma-requests = <27>;
436 #dma-cells = <1>;
439 tcon0: lcd-controller@1c0c000 {
440 compatible = "allwinner,sun50i-a64-tcon-lcd",
441 "allwinner,sun8i-a83t-tcon-lcd";
445 clock-names = "ahb", "tcon-ch0";
446 clock-output-names = "tcon-data-clock";
447 #clock-cells = <0>;
449 reset-names = "lcd", "lvds";
452 #address-cells = <1>;
453 #size-cells = <0>;
456 #address-cells = <1>;
457 #size-cells = <0>;
462 remote-endpoint = <&mixer0_out_tcon0>;
467 remote-endpoint = <&mixer1_out_tcon0>;
472 #address-cells = <1>;
473 #size-cells = <0>;
478 remote-endpoint = <&dsi_in_tcon0>;
479 allwinner,tcon-channel = <1>;
485 tcon1: lcd-controller@1c0d000 {
486 compatible = "allwinner,sun50i-a64-tcon-tv",
487 "allwinner,sun8i-a83t-tcon-tv";
491 clock-names = "ahb", "tcon-ch1";
493 reset-names = "lcd";
496 #address-cells = <1>;
497 #size-cells = <0>;
500 #address-cells = <1>;
501 #size-cells = <0>;
506 remote-endpoint = <&mixer0_out_tcon1>;
511 remote-endpoint = <&mixer1_out_tcon1>;
516 #address-cells = <1>;
517 #size-cells = <0>;
522 remote-endpoint = <&hdmi_in_tcon1>;
528 video-codec@1c0e000 {
529 compatible = "allwinner,sun50i-a64-video-engine";
533 clock-names = "ahb", "mod", "ram";
540 compatible = "allwinner,sun50i-a64-mmc";
543 clock-names = "ahb", "mmc";
545 reset-names = "ahb";
547 max-frequency = <150000000>;
549 #address-cells = <1>;
550 #size-cells = <0>;
554 compatible = "allwinner,sun50i-a64-mmc";
557 clock-names = "ahb", "mmc";
559 reset-names = "ahb";
561 max-frequency = <150000000>;
563 #address-cells = <1>;
564 #size-cells = <0>;
568 compatible = "allwinner,sun50i-a64-emmc";
571 clock-names = "ahb", "mmc";
573 reset-names = "ahb";
575 max-frequency = <150000000>;
577 #address-cells = <1>;
578 #size-cells = <0>;
582 compatible = "allwinner,sun50i-a64-sid";
584 #address-cells = <1>;
585 #size-cells = <1>;
587 ths_calibration: thermal-sensor-calibration@34 {
593 compatible = "allwinner,sun50i-a64-crypto";
597 clock-names = "bus", "mod";
602 compatible = "allwinner,sun50i-a64-msgbox",
603 "allwinner,sun6i-a31-msgbox";
608 #mbox-cells = <1>;
612 compatible = "allwinner,sun8i-a33-musb";
617 interrupt-names = "mc";
619 phy-names = "usb";
621 dr_mode = "otg";
626 compatible = "allwinner,sun50i-a64-usb-phy";
630 reg-names = "phy_ctrl",
635 clock-names = "usb0_phy",
639 reset-names = "usb0_reset",
642 #phy-cells = <1>;
646 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
655 phy-names = "usb";
660 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
667 phy-names = "usb";
672 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
681 phy-names = "usb";
686 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
693 phy-names = "usb";
698 compatible = "allwinner,sun50i-a64-ccu";
701 clock-names = "hosc", "losc";
702 #clock-cells = <1>;
703 #reset-cells = <1>;
707 compatible = "allwinner,sun50i-a64-pinctrl";
709 interrupt-parent = <&r_intc>;
715 clock-names = "apb", "hosc", "losc";
716 gpio-controller;
717 #gpio-cells = <3>;
718 interrupt-controller;
719 #interrupt-cells = <3>;
721 /omit-if-no-ref/
722 aif2_pins: aif2-pins {
723 pins = "PB4", "PB5", "PB6", "PB7";
727 /omit-if-no-ref/
728 aif3_pins: aif3-pins {
729 pins = "PG10", "PG11", "PG12", "PG13";
733 csi_pins: csi-pins {
734 pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
739 /omit-if-no-ref/
740 csi_mclk_pin: csi-mclk-pin {
741 pins = "PE1";
745 i2c0_pins: i2c0-pins {
746 pins = "PH0", "PH1";
750 i2c1_pins: i2c1-pins {
751 pins = "PH2", "PH3";
755 i2c2_pins: i2c2-pins {
756 pins = "PE14", "PE15";
760 /omit-if-no-ref/
761 lcd_rgb666_pins: lcd-rgb666-pins {
762 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
770 mmc0_pins: mmc0-pins {
771 pins = "PF0", "PF1", "PF2", "PF3",
774 drive-strength = <30>;
775 bias-pull-up;
778 mmc1_pins: mmc1-pins {
779 pins = "PG0", "PG1", "PG2", "PG3",
782 drive-strength = <30>;
783 bias-pull-up;
786 mmc2_pins: mmc2-pins {
787 pins = "PC5", "PC6", "PC8", "PC9",
791 drive-strength = <30>;
792 bias-pull-up;
795 mmc2_ds_pin: mmc2-ds-pin {
796 pins = "PC1";
798 drive-strength = <30>;
799 bias-pull-up;
802 pwm_pin: pwm-pin {
803 pins = "PD22";
807 rmii_pins: rmii-pins {
808 pins = "PD10", "PD11", "PD13", "PD14", "PD17",
811 drive-strength = <40>;
814 rgmii_pins: rgmii-pins {
815 pins = "PD8", "PD9", "PD10", "PD11", "PD12",
819 drive-strength = <40>;
822 spdif_tx_pin: spdif-tx-pin {
823 pins = "PH8";
827 spi0_pins: spi0-pins {
828 pins = "PC0", "PC1", "PC2", "PC3";
832 spi1_pins: spi1-pins {
833 pins = "PD0", "PD1", "PD2", "PD3";
837 uart0_pb_pins: uart0-pb-pins {
838 pins = "PB8", "PB9";
842 uart1_pins: uart1-pins {
843 pins = "PG6", "PG7";
847 uart1_rts_cts_pins: uart1-rts-cts-pins {
848 pins = "PG8", "PG9";
852 uart2_pins: uart2-pins {
853 pins = "PB0", "PB1";
857 uart3_pins: uart3-pins {
858 pins = "PD0", "PD1";
862 uart4_pins: uart4-pins {
863 pins = "PD2", "PD3";
867 uart4_rts_cts_pins: uart4-rts-cts-pins {
868 pins = "PD4", "PD5";
874 compatible = "allwinner,sun50i-a64-timer",
875 "allwinner,sun8i-a23-timer";
883 compatible = "allwinner,sun50i-a64-wdt",
884 "allwinner,sun6i-a31-wdt";
891 #sound-dai-cells = <0>;
892 compatible = "allwinner,sun50i-a64-spdif",
893 "allwinner,sun8i-h3-spdif";
898 clock-names = "apb", "spdif";
900 dma-names = "tx";
901 pinctrl-names = "default";
902 pinctrl-0 = <&spdif_tx_pin>;
907 compatible = "allwinner,sun50i-a64-lradc",
908 "allwinner,sun8i-a83t-r-lradc";
910 interrupt-parent = <&r_intc>;
916 #sound-dai-cells = <0>;
917 compatible = "allwinner,sun50i-a64-i2s",
918 "allwinner,sun8i-h3-i2s";
922 clock-names = "apb", "mod";
924 dma-names = "rx", "tx";
930 #sound-dai-cells = <0>;
931 compatible = "allwinner,sun50i-a64-i2s",
932 "allwinner,sun8i-h3-i2s";
936 clock-names = "apb", "mod";
938 dma-names = "rx", "tx";
944 #sound-dai-cells = <0>;
945 compatible = "allwinner,sun50i-a64-i2s",
946 "allwinner,sun8i-h3-i2s";
950 clock-names = "apb", "mod";
952 dma-names = "rx", "tx";
958 #sound-dai-cells = <0>;
959 compatible = "allwinner,sun50i-a64-codec-i2s";
963 clock-names = "apb", "mod";
966 dma-names = "rx", "tx";
971 #sound-dai-cells = <1>;
972 compatible = "allwinner,sun50i-a64-codec",
973 "allwinner,sun8i-a33-codec";
977 clock-names = "bus", "mod";
981 ths: thermal-sensor@1c25000 {
982 compatible = "allwinner,sun50i-a64-ths";
985 clock-names = "bus", "mod";
988 nvmem-cells = <&ths_calibration>;
989 nvmem-cell-names = "calibration";
990 #thermal-sensor-cells = <1>;
994 compatible = "snps,dw-apb-uart";
997 reg-shift = <2>;
998 reg-io-width = <4>;
1005 compatible = "snps,dw-apb-uart";
1008 reg-shift = <2>;
1009 reg-io-width = <4>;
1016 compatible = "snps,dw-apb-uart";
1019 reg-shift = <2>;
1020 reg-io-width = <4>;
1027 compatible = "snps,dw-apb-uart";
1030 reg-shift = <2>;
1031 reg-io-width = <4>;
1038 compatible = "snps,dw-apb-uart";
1041 reg-shift = <2>;
1042 reg-io-width = <4>;
1049 compatible = "allwinner,sun6i-a31-i2c";
1054 pinctrl-names = "default";
1055 pinctrl-0 = <&i2c0_pins>;
1057 #address-cells = <1>;
1058 #size-cells = <0>;
1062 compatible = "allwinner,sun6i-a31-i2c";
1067 pinctrl-names = "default";
1068 pinctrl-0 = <&i2c1_pins>;
1070 #address-cells = <1>;
1071 #size-cells = <0>;
1075 compatible = "allwinner,sun6i-a31-i2c";
1080 pinctrl-names = "default";
1081 pinctrl-0 = <&i2c2_pins>;
1083 #address-cells = <1>;
1084 #size-cells = <0>;
1088 compatible = "allwinner,sun8i-h3-spi";
1092 clock-names = "ahb", "mod";
1094 dma-names = "rx", "tx";
1095 pinctrl-names = "default";
1096 pinctrl-0 = <&spi0_pins>;
1099 num-cs = <1>;
1100 #address-cells = <1>;
1101 #size-cells = <0>;
1105 compatible = "allwinner,sun8i-h3-spi";
1109 clock-names = "ahb", "mod";
1111 dma-names = "rx", "tx";
1112 pinctrl-names = "default";
1113 pinctrl-0 = <&spi1_pins>;
1116 num-cs = <1>;
1117 #address-cells = <1>;
1118 #size-cells = <0>;
1122 compatible = "allwinner,sun50i-a64-emac";
1126 interrupt-names = "macirq";
1128 reset-names = "stmmaceth";
1130 clock-names = "stmmaceth";
1134 compatible = "snps,dwmac-mdio";
1135 #address-cells = <1>;
1136 #size-cells = <0>;
1141 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400";
1150 interrupt-names = "gp",
1158 clock-names = "bus", "core";
1160 operating-points-v2 = <&gpu_opp_table>;
1163 gic: interrupt-controller@1c81000 {
1164 compatible = "arm,gic-400";
1170 interrupt-controller;
1171 #interrupt-cells = <3>;
1175 compatible = "allwinner,sun50i-a64-pwm",
1176 "allwinner,sun5i-a13-pwm";
1179 pinctrl-names = "default";
1180 pinctrl-0 = <&pwm_pin>;
1181 #pwm-cells = <3>;
1185 mbus: dram-controller@1c62000 {
1186 compatible = "allwinner,sun50i-a64-mbus";
1189 reg-names = "mbus", "dram";
1193 clock-names = "mbus", "dram", "bus";
1195 #address-cells = <1>;
1196 #size-cells = <1>;
1197 dma-ranges = <0x00000000 0x40000000 0xc0000000>;
1198 #interconnect-cells = <1>;
1202 compatible = "allwinner,sun50i-a64-csi";
1208 clock-names = "bus", "mod", "ram";
1210 pinctrl-names = "default";
1211 pinctrl-0 = <&csi_pins>;
1216 compatible = "allwinner,sun50i-a64-mipi-dsi";
1222 phy-names = "dphy";
1224 #address-cells = <1>;
1225 #size-cells = <0>;
1229 remote-endpoint = <&tcon0_out_dsi>;
1234 dphy: d-phy@1ca1000 {
1235 compatible = "allwinner,sun50i-a64-mipi-dphy",
1236 "allwinner,sun6i-a31-mipi-dphy";
1241 clock-names = "bus", "mod";
1244 #phy-cells = <0>;
1248 compatible = "allwinner,sun50i-a64-deinterlace",
1249 "allwinner,sun8i-h3-deinterlace";
1254 clock-names = "bus", "mod", "ram";
1258 interconnect-names = "dma-mem";
1262 compatible = "allwinner,sun50i-a64-dw-hdmi",
1263 "allwinner,sun8i-a83t-dw-hdmi";
1265 reg-io-width = <1>;
1269 clock-names = "iahb", "isfr", "tmds", "cec";
1271 reset-names = "ctrl";
1273 phy-names = "phy";
1277 #address-cells = <1>;
1278 #size-cells = <0>;
1284 remote-endpoint = <&tcon1_out_hdmi>;
1294 hdmi_phy: hdmi-phy@1ef0000 {
1295 compatible = "allwinner,sun50i-a64-hdmi-phy";
1299 clock-names = "bus", "mod", "pll-0";
1301 reset-names = "phy";
1302 #phy-cells = <0>;
1306 compatible = "allwinner,sun50i-a64-rtc",
1307 "allwinner,sun8i-h3-rtc";
1309 interrupt-parent = <&r_intc>;
1312 clock-output-names = "osc32k", "osc32k-out", "iosc";
1314 #clock-cells = <1>;
1317 r_intc: interrupt-controller@1f00c00 {
1318 compatible = "allwinner,sun50i-a64-r-intc",
1319 "allwinner,sun6i-a31-r-intc";
1320 interrupt-controller;
1321 #interrupt-cells = <3>;
1327 compatible = "allwinner,sun50i-a64-r-ccu";
1331 clock-names = "hosc", "losc", "iosc", "pll-periph";
1332 #clock-cells = <1>;
1333 #reset-cells = <1>;
1336 codec_analog: codec-analog@1f015c0 {
1337 compatible = "allwinner,sun50i-a64-codec-analog";
1343 compatible = "allwinner,sun50i-a64-i2c",
1344 "allwinner,sun6i-a31-i2c";
1350 #address-cells = <1>;
1351 #size-cells = <0>;
1355 compatible = "allwinner,sun50i-a64-ir",
1356 "allwinner,sun6i-a31-ir";
1359 clock-names = "apb", "ir";
1362 pinctrl-names = "default";
1363 pinctrl-0 = <&r_ir_rx_pin>;
1368 compatible = "allwinner,sun50i-a64-pwm",
1369 "allwinner,sun5i-a13-pwm";
1372 pinctrl-names = "default";
1373 pinctrl-0 = <&r_pwm_pin>;
1374 #pwm-cells = <3>;
1379 compatible = "allwinner,sun50i-a64-r-pinctrl";
1381 interrupt-parent = <&r_intc>;
1384 clock-names = "apb", "hosc", "losc";
1385 gpio-controller;
1386 #gpio-cells = <3>;
1387 interrupt-controller;
1388 #interrupt-cells = <3>;
1390 r_i2c_pl89_pins: r-i2c-pl89-pins {
1391 pins = "PL8", "PL9";
1395 r_ir_rx_pin: r-ir-rx-pin {
1396 pins = "PL11";
1400 r_pwm_pin: r-pwm-pin {
1401 pins = "PL10";
1405 r_rsb_pins: r-rsb-pins {
1406 pins = "PL0", "PL1";
1412 compatible = "allwinner,sun8i-a23-rsb";
1416 clock-frequency = <3000000>;
1418 pinctrl-names = "default";
1419 pinctrl-0 = <&r_rsb_pins>;
1421 #address-cells = <1>;
1422 #size-cells = <0>;