Lines Matching +full:0 +full:x05100000
12 #define ARM_R0 0
29 #define ARM_COND_EQ 0x0 /* == */
30 #define ARM_COND_NE 0x1 /* != */
31 #define ARM_COND_CS 0x2 /* unsigned >= */
33 #define ARM_COND_CC 0x3 /* unsigned < */
35 #define ARM_COND_MI 0x4 /* < 0 */
36 #define ARM_COND_PL 0x5 /* >= 0 */
37 #define ARM_COND_VS 0x6 /* Signed Overflow */
38 #define ARM_COND_VC 0x7 /* No Signed Overflow */
39 #define ARM_COND_HI 0x8 /* unsigned > */
40 #define ARM_COND_LS 0x9 /* unsigned <= */
41 #define ARM_COND_GE 0xa /* Signed >= */
42 #define ARM_COND_LT 0xb /* Signed < */
43 #define ARM_COND_GT 0xc /* Signed > */
44 #define ARM_COND_LE 0xd /* Signed <= */
45 #define ARM_COND_AL 0xe /* None */
48 #define SRTYPE_LSL 0
54 #define ARM_INST_ADD_R 0x00800000
55 #define ARM_INST_ADDS_R 0x00900000
56 #define ARM_INST_ADC_R 0x00a00000
57 #define ARM_INST_ADC_I 0x02a00000
58 #define ARM_INST_ADD_I 0x02800000
59 #define ARM_INST_ADDS_I 0x02900000
61 #define ARM_INST_AND_R 0x00000000
62 #define ARM_INST_ANDS_R 0x00100000
63 #define ARM_INST_AND_I 0x02000000
65 #define ARM_INST_BIC_R 0x01c00000
66 #define ARM_INST_BIC_I 0x03c00000
68 #define ARM_INST_B 0x0a000000
69 #define ARM_INST_BX 0x012FFF10
70 #define ARM_INST_BLX_R 0x012fff30
72 #define ARM_INST_CMP_R 0x01500000
73 #define ARM_INST_CMP_I 0x03500000
75 #define ARM_INST_EOR_R 0x00200000
76 #define ARM_INST_EOR_I 0x02200000
78 #define ARM_INST_LDST__U 0x00800000
79 #define ARM_INST_LDST__IMM12 0x00000fff
80 #define ARM_INST_LDRB_I 0x05500000
81 #define ARM_INST_LDRB_R 0x07d00000
82 #define ARM_INST_LDRSB_I 0x015000d0
83 #define ARM_INST_LDRD_I 0x014000d0
84 #define ARM_INST_LDRH_I 0x015000b0
85 #define ARM_INST_LDRH_R 0x019000b0
86 #define ARM_INST_LDRSH_I 0x015000f0
87 #define ARM_INST_LDR_I 0x05100000
88 #define ARM_INST_LDR_R 0x07900000
90 #define ARM_INST_LDM 0x08900000
91 #define ARM_INST_LDM_IA 0x08b00000
93 #define ARM_INST_LSL_I 0x01a00000
94 #define ARM_INST_LSL_R 0x01a00010
96 #define ARM_INST_LSR_I 0x01a00020
97 #define ARM_INST_LSR_R 0x01a00030
99 #define ARM_INST_ASR_I 0x01a00040
100 #define ARM_INST_ASR_R 0x01a00050
102 #define ARM_INST_MOV_R 0x01a00000
103 #define ARM_INST_MOVS_R 0x01b00000
104 #define ARM_INST_MOV_I 0x03a00000
105 #define ARM_INST_MOVW 0x03000000
106 #define ARM_INST_MOVT 0x03400000
108 #define ARM_INST_MUL 0x00000090
110 #define ARM_INST_POP 0x08bd0000
111 #define ARM_INST_PUSH 0x092d0000
113 #define ARM_INST_ORR_R 0x01800000
114 #define ARM_INST_ORRS_R 0x01900000
115 #define ARM_INST_ORR_I 0x03800000
117 #define ARM_INST_REV 0x06bf0f30
118 #define ARM_INST_REV16 0x06bf0fb0
120 #define ARM_INST_RSB_I 0x02600000
121 #define ARM_INST_RSBS_I 0x02700000
122 #define ARM_INST_RSC_I 0x02e00000
124 #define ARM_INST_SUB_R 0x00400000
125 #define ARM_INST_SUBS_R 0x00500000
126 #define ARM_INST_RSB_R 0x00600000
127 #define ARM_INST_SUB_I 0x02400000
128 #define ARM_INST_SUBS_I 0x02500000
129 #define ARM_INST_SBC_I 0x02c00000
130 #define ARM_INST_SBC_R 0x00c00000
131 #define ARM_INST_SBCS_R 0x00d00000
133 #define ARM_INST_STR_I 0x05000000
134 #define ARM_INST_STRB_I 0x05400000
135 #define ARM_INST_STRD_I 0x014000f0
136 #define ARM_INST_STRH_I 0x014000b0
138 #define ARM_INST_TST_R 0x01100000
139 #define ARM_INST_TST_I 0x03100000
141 #define ARM_INST_UDIV 0x0730f010
142 #define ARM_INST_SDIV 0x0710f010
144 #define ARM_INST_UMULL 0x00800090
146 #define ARM_INST_MLS 0x00600090
148 #define ARM_INST_UXTH 0x06ff0070
162 #define ARM_INST_UDF 0xe7fddef1
185 #define ARM_B(imm24) (ARM_INST_B | ((imm24) & 0xffffff))
189 #define ARM_CMP_R(rn, rm) _AL3_R(ARM_INST_CMP, 0, rn, rm)
190 #define ARM_CMP_I(rn, imm) _AL3_I(ARM_INST_CMP, 0, rn, imm)
212 #define ARM_LSL_R(rd, rn, rm) (_AL3_R(ARM_INST_LSL, rd, 0, rn) | (rm) << 8)
213 #define ARM_LSL_I(rd, rn, imm) (_AL3_I(ARM_INST_LSL, rd, 0, rn) | (imm) << 7)
215 #define ARM_LSR_R(rd, rn, rm) (_AL3_R(ARM_INST_LSR, rd, 0, rn) | (rm) << 8)
216 #define ARM_LSR_I(rd, rn, imm) (_AL3_I(ARM_INST_LSR, rd, 0, rn) | (imm) << 7)
217 #define ARM_ASR_R(rd, rn, rm) (_AL3_R(ARM_INST_ASR, rd, 0, rn) | (rm) << 8)
218 #define ARM_ASR_I(rd, rn, imm) (_AL3_I(ARM_INST_ASR, rd, 0, rn) | (imm) << 7)
220 #define ARM_MOV_R(rd, rm) _AL3_R(ARM_INST_MOV, rd, 0, rm)
221 #define ARM_MOVS_R(rd, rm) _AL3_R(ARM_INST_MOVS, rd, 0, rm)
222 #define ARM_MOV_I(rd, imm) _AL3_I(ARM_INST_MOV, rd, 0, imm)
229 (ARM_INST_MOVW | ((imm) >> 12) << 16 | (rd) << 12 | ((imm) & 0x0fff))
232 (ARM_INST_MOVT | ((imm) >> 12) << 16 | (rd) << 12 | ((imm) & 0x0fff))
267 #define ARM_TST_R(rn, rm) _AL3_R(ARM_INST_TST, 0, rn, rm)
268 #define ARM_TST_I(rn, imm) _AL3_I(ARM_INST_TST, 0, rn, imm)