Lines Matching +full:2 +full:c0
57 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
69 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
91 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
94 mcr p15, 0, r0, c1, c0, 0 @ disable caches
112 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
115 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
118 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
140 mcr p14, 0, r0, c7, c0, 0 @ go to idle
373 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
396 .long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED
425 mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode
427 mrc p15, 0, r6, c13, c0, 0 @ PID
428 mrc p15, 0, r7, c3, c0, 0 @ domain ID
429 mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg
430 mrc p15, 0, r9, c1, c0, 0 @ control reg
431 bic r4, r4, #2 @ clear frequency change bit
443 mcr p14, 0, r4, c6, c0, 0 @ clock configuration, turbo mode.
445 mcr p15, 0, r6, c13, c0, 0 @ PID
446 mcr p15, 0, r7, c3, c0, 0 @ domain ID
448 mcr p15, 0, r1, c2, c0, 0 @ translation table base addr
449 mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg
464 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
469 mrc p15, 0, r0, c1, c0, 1 @ get auxiliary control reg
470 and r0, r0, #2 @ preserve bit P bit setting
472 mcr p15, 0, r0, c1, c0, 1 @ set auxiliary control reg
478 mrc p15, 1, r0, c0, c0, 1 @ get L2 present information
483 mrc p15, 0, r0, c1, c0, 0 @ get control register