Lines Matching +full:entry +full:- +full:address
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/arm946.S: utility functions for ARM946E-S
5 * Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com)
7 * (Many of cache codes are from proc-arm926.S)
15 #include <asm/pgtable-hwdef.h>
17 #include "proc-macros.S"
20 * ARM946E-S is synthesizable to have 0KB to 1MB sized D-Cache,
49 bic r0, r0, #0x00001000 @ i-cache
50 bic r0, r0, #0x00000004 @ d-cache
57 * Params : r0 = address to jump to
68 bic ip, ip, #0x00001000 @ i-cache
111 mov r1, #(CACHE_DSEGMENTS - 1) << 29 @ 4 segments
112 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 4 @ n entries
129 * specified address range.
131 * - start - start address (inclusive)
132 * - end - end address (exclusive)
133 * - flags - vm_flags describing address space
144 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
145 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
147 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
148 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
151 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
152 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
154 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
155 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
169 * region described by start, end. If you have non-snooping
172 * - start - virtual start address
173 * - end - virtual end address
185 * region described by start, end. If you have non-snooping
188 * - start - virtual start address
189 * - end - virtual end address
193 bic r0, r0, #CACHE_DLINESIZE - 1
194 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
195 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
210 * - addr - kernel address
211 * - size - region size
216 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
229 * Invalidate (discard) the specified virtual address range.
234 * - start - virtual start address
235 * - end - virtual end address
240 tst r0, #CACHE_DLINESIZE - 1
241 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
242 tst r1, #CACHE_DLINESIZE - 1
243 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
245 bic r0, r0, #CACHE_DLINESIZE - 1
246 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
256 * Clean the specified virtual address range.
258 * - start - virtual start address
259 * - end - virtual end address
265 bic r0, r0, #CACHE_DLINESIZE - 1
266 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
277 * Clean and invalidate the specified virtual address range.
279 * - start - virtual start address
280 * - end - virtual end address
285 bic r0, r0, #CACHE_DLINESIZE - 1
288 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
290 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
301 * - start - kernel virtual start address
302 * - size - size of region
303 * - dir - DMA direction
315 * - start - kernel virtual start address
316 * - size - size of region
317 * - dir - DMA direction
325 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
361 mcr p15, 0, r0, c2, c0, 0 @ region 1,2 d-cacheable
362 mcr p15, 0, r0, c2, c0, 1 @ region 1,2 i-cacheable
374 * region 0 (whole) rw -- : b0001
376 * region 2 (FLASH) rw r- : b0010
377 * region 3~7 (none) -- -- : b0000
385 orr r0, r0, #0x00001000 @ I-cache
386 orr r0, r0, #0x00000005 @ MPU/D-cache
392 .size __arm946_setup, . - __arm946_setup
396 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
403 string cpu_arm946_name, "ARM946E-S"
423 .size __arm946_proc_info, . - __arm946_proc_info