Lines Matching +full:entry +full:- +full:address
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 * Copyright (C) 2002-2003 MontaVista Software, Inc.
10 * Update for Linux-2.6 and cache flush improvements
13 * hacked for non-paged-MM by Hyok S. Choi, 2004.
18 * CONFIG_CPU_ARM925_CPU_IDLE -> nohlt
20 * Some additional notes based on deciphering the TI TRM on OMAP-5910:
22 * NOTE1: The TI925T Configuration Register bit "D-cache clean and flush
23 * entry mode" must be 0 to flush the entries in both segments
24 * at once. This is the default value. See TRM 2-20 and 2-24 for
27 * NOTE2: Default is the "D-cache clean and flush entry mode". It looks
29 * to work in this mode. This mode only works with 16-bit external
30 * memory. See TRM 2-24 for more information.
32 * NOTE3: Write-back cache flushing seems to be flakey with devices using
34 * write-through cache with CONFIG_CPU_DCACHE_WRITETHROUGH (this is
35 * the default for OMAP-1510).
44 #include <asm/pgtable-hwdef.h>
47 #include "proc-macros.S"
155 * address space.
172 mov r3, #(CACHE_DENTRIES - 1) << 4 @ 256 entries in segment
187 * specified address range.
189 * - start - start address (inclusive)
190 * - end - end address (exclusive)
191 * - flags - vm_flags describing address space
200 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
201 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
203 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
204 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
207 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
208 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
210 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
211 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
225 * region described by start, end. If you have non-snooping
228 * - start - virtual start address
229 * - end - virtual end address
241 * region described by start, end. If you have non-snooping
244 * - start - virtual start address
245 * - end - virtual end address
248 bic r0, r0, #CACHE_DLINESIZE - 1
249 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
250 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
265 * - addr - kernel address
266 * - size - region size
270 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
283 * Invalidate (discard) the specified virtual address range.
288 * - start - virtual start address
289 * - end - virtual end address
295 tst r0, #CACHE_DLINESIZE - 1
296 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
297 tst r1, #CACHE_DLINESIZE - 1
298 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
300 bic r0, r0, #CACHE_DLINESIZE - 1
301 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
311 * Clean the specified virtual address range.
313 * - start - virtual start address
314 * - end - virtual end address
320 bic r0, r0, #CACHE_DLINESIZE - 1
321 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
332 * Clean and invalidate the specified virtual address range.
334 * - start - virtual start address
335 * - end - virtual end address
338 bic r0, r0, #CACHE_DLINESIZE - 1
341 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
343 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
354 * - start - kernel virtual start address
355 * - size - size of region
356 * - dir - DMA direction
368 * - start - kernel virtual start address
369 * - size - size of region
370 * - dir - DMA direction
378 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
404 mov r3, #(CACHE_DENTRIES - 1) << 4 @ 256 entries in segment
428 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
439 /* Transparent on, D-cache clean & flush mode. See NOTE2 above */
451 mov r0, #4 @ disable write-back on caches explicitly
464 .size __arm925_setup, . - __arm925_setup
477 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
513 .size __\name\()_proc_info, . - __\name\()_proc_info