Lines Matching +full:armv4t +full:- +full:based

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8  *  Copyright (C) 2002-2003 MontaVista Software, Inc.
10  *  Update for Linux-2.6 and cache flush improvements
13  *  hacked for non-paged-MM by Hyok S. Choi, 2004.
18  *  CONFIG_CPU_ARM925_CPU_IDLE -> nohlt
20  * Some additional notes based on deciphering the TI TRM on OMAP-5910:
22  * NOTE1: The TI925T Configuration Register bit "D-cache clean and flush
24  *	  at once. This is the default value. See TRM 2-20 and 2-24 for
27  * NOTE2: Default is the "D-cache clean and flush entry mode". It looks
29  *	  to work in this mode. This mode only works with 16-bit external
30  *	  memory. See TRM 2-24 for more information.
32  * NOTE3: Write-back cache flushing seems to be flakey with devices using
34  *        write-through cache with CONFIG_CPU_DCACHE_WRITETHROUGH (this is
35  *        the default for OMAP-1510).
44 #include <asm/pgtable-hwdef.h>
47 #include "proc-macros.S"
172 	mov	r3, #(CACHE_DENTRIES - 1) << 4	@ 256 entries in segment
189  *	- start	- start address (inclusive)
190  *	- end	- end address (exclusive)
191  *	- flags	- vm_flags describing address space
225  *	region described by start, end.  If you have non-snooping
228  *	- start	- virtual start address
229  *	- end	- virtual end address
241  *	region described by start, end.  If you have non-snooping
244  *	- start	- virtual start address
245  *	- end	- virtual end address
248 	bic	r0, r0, #CACHE_DLINESIZE - 1
265  *	- addr	- kernel address
266  *	- size	- region size
288  *	- start	- virtual start address
289  *	- end	- virtual end address
295 	tst	r0, #CACHE_DLINESIZE - 1
297 	tst	r1, #CACHE_DLINESIZE - 1
300 	bic	r0, r0, #CACHE_DLINESIZE - 1
313  *	- start	- virtual start address
314  *	- end	- virtual end address
320 	bic	r0, r0, #CACHE_DLINESIZE - 1
334  *	- start	- virtual start address
335  *	- end	- virtual end address
338 	bic	r0, r0, #CACHE_DLINESIZE - 1
354  *	- start	- kernel virtual start address
355  *	- size	- size of region
356  *	- dir	- DMA direction
368  *	- start	- kernel virtual start address
369  *	- size	- size of region
370  *	- dir	- DMA direction
404 	mov	r3, #(CACHE_DENTRIES - 1) << 4	@ 256 entries in segment
439 	/* Transparent on, D-cache clean & flush mode. See  NOTE2 above */
451 	mov	r0, #4				@ disable write-back on caches explicitly
464 	.size	__arm925_setup, . - __arm925_setup
477 	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
482 	string	cpu_arch_name, "armv4t"
513 	.size	__\name\()_proc_info, . - __\name\()_proc_info