25 .macro v7m_cache_read, rt, reg
26 	movw	\rt, #:lower16:BASEADDR_V7M_SCB + \reg
27 	movt	\rt, #:upper16:BASEADDR_V7M_SCB + \reg
28 	ldr     \rt, [\rt]
31 .macro v7m_cacheop, rt, tmp, op, c = al
34 	str\c	\rt, [\tmp]
38 .macro	read_ccsidr, rt  argument
39 	v7m_cache_read \rt, V7M_SCB_CCSIDR
42 .macro read_clidr, rt  argument
43 	v7m_cache_read \rt, V7M_SCB_CLIDR
46 .macro	write_csselr, rt, tmp
47 	v7m_cacheop \rt, \tmp, V7M_SCB_CSSELR
53 .macro dcisw, rt, tmp
54 	v7m_cacheop \rt, \tmp, V7M_SCB_DCISW
60 .macro dccisw, rt, tmp
61 	v7m_cacheop \rt, \tmp, V7M_SCB_DCCISW
68 .macro dccimvac\c, rt, tmp
69 	v7m_cacheop \rt, \tmp, V7M_SCB_DCCIMVAC, \c
77 .macro dcimvac\c, rt, tmp
78 	v7m_cacheop \rt, \tmp, V7M_SCB_DCIMVAC, \c
85 .macro dccmvau, rt, tmp
86 	v7m_cacheop \rt, \tmp, V7M_SCB_DCCMVAU
92 .macro dccmvac,  rt, tmp
93 	v7m_cacheop \rt, \tmp, V7M_SCB_DCCMVAC
99 .macro icimvau, rt, tmp
100 	v7m_cacheop \rt, \tmp, V7M_SCB_ICIMVAU
107 .macro invalidate_icache, rt  argument
108 	v7m_cacheop \rt, \rt, V7M_SCB_ICIALLU
109 	mov \rt, #0
116 .macro invalidate_bp, rt  argument
117 	v7m_cacheop \rt, \rt, V7M_SCB_BPIALL
118 	mov \rt, #0