Lines Matching full:l2c
160 * L2C-210 specific code.
162 * The L2C-2x0 PA, set/way and sync operations are atomic, but we must
171 * we use sync_reg_offset here so we can share some of this with L2C-310.
240 .type = "L2C-210",
259 * L2C-220 specific code.
390 * we write to them as part of the L2C enable sequence so they in l2c220_enable()
405 .type = "L2C-220",
424 * L2C-310 specific code.
426 * Very similar to L2C-210, the PA, set/way and sync operations are atomic,
460 * prevents merging writes after the sync operation, until another L2C
616 pr_info("L2C-310 enabling early BRESP for Cortex-A9\n"); in l2c310_enable()
618 pr_warn("L2C-310 early BRESP only supported with Cortex-A9\n"); in l2c310_enable()
630 pr_err("L2C-310: full line of zeros enabled in Cortex-A9 but not L2C-310 - invalid\n"); in l2c310_enable()
633 pr_err("L2C-310: enabling full line of zeros but not enabled in Cortex-A9\n"); in l2c310_enable()
637 pr_info("L2C-310 full line of zeros enabled for Cortex-A9\n"); in l2c310_enable()
640 pr_err("L2C-310: disabling Cortex-A9 specific feature bits\n"); in l2c310_enable()
646 * we write to them as part of the L2C enable sequence so they in l2c310_enable()
659 pr_info("L2C-310 %s%s prefetch enabled, offset %u lines\n", in l2c310_enable()
670 pr_info("L2C-310 dynamic clock gating %sabled, standby mode %sabled\n", in l2c310_enable()
726 pr_info("L2C-310 errat%s", n > 1 ? "a" : "um"); in l2c310_fixup()
761 .type = "L2C-310",
801 pr_alert("L2C: platform provided aux values permit register corruption.\n"); in __l2c_init()
808 pr_warn("L2C: DT/platform modifies aux control register: 0x%08x -> 0x%08x\n", in __l2c_init()
815 pr_warn("L2C: DT/platform tries to modify or specify cache size\n"); in __l2c_init()
858 pr_info("L2C: disabling outer sync\n"); in __l2c_init()
969 pr_warn("L2C OF: no cache block/line size given: " in l2x0_cache_size_of_parse()
977 pr_warn("L2C OF: DT supplied line size %d bytes does " in l2x0_cache_size_of_parse()
994 pr_err("L2C OF: set size %dKB is too large\n", way_size); in l2x0_cache_size_of_parse()
998 pr_info("L2C OF: override cache size: %d bytes (%dKB)\n", in l2x0_cache_size_of_parse()
1000 pr_info("L2C OF: override line size: %d bytes\n", line_size); in l2x0_cache_size_of_parse()
1001 pr_info("L2C OF: override way size: %d bytes (%dKB)\n", in l2x0_cache_size_of_parse()
1003 pr_info("L2C OF: override associativity: %d\n", *associativity); in l2x0_cache_size_of_parse()
1011 pr_err("L2C OF: cache way size illegal: %dKB is not mapped\n", in l2x0_cache_size_of_parse()
1087 .type = "L2C-210",
1107 .type = "L2C-220",
1175 pr_err("L2C-310 OF cache associativity %d invalid, only 8 or 16 permitted\n", in l2c310_of_parse()
1209 pr_err("L2C-310 OF arm,double-linefill property value is missing\n"); in l2c310_of_parse()
1219 pr_err("L2C-310 OF arm,double-linefill-incr property value is missing\n"); in l2c310_of_parse()
1229 pr_err("L2C-310 OF arm,double-linefill-wrap property value is missing\n"); in l2c310_of_parse()
1239 pr_err("L2C-310 OF arm,prefetch-drop property value is missing\n"); in l2c310_of_parse()
1247 pr_err("L2C-310 OF arm,prefetch-offset property value is missing\n"); in l2c310_of_parse()
1261 pr_err("L2C-310 OF prefetch-data property value is missing\n"); in l2c310_of_parse()
1275 pr_err("L2C-310 OF prefetch-instr property value is missing\n"); in l2c310_of_parse()
1288 pr_err("L2C-310 OF dynamic-clock-gating property value is missing or invalid\n"); in l2c310_of_parse()
1295 pr_err("L2C-310 OF standby-mode property value is missing or invalid\n"); in l2c310_of_parse()
1302 .type = "L2C-310",
1332 .type = "L2C-310 Coherent",
1693 /* Broadcom L2C-310 start from ARMs R3P2 or later, and require no fixups */
1695 .type = "BCM-L2C-310",
1791 pr_warn("L2C: platform modifies aux control register: 0x%08x -> 0x%08x\n", in l2x0_of_init()
1794 …pr_alert("L2C: platform provided aux values match the hardware, so have no effect. Please remove … in l2x0_of_init()
1799 pr_err("L2C: device tree omits to specify unified cache\n"); in l2x0_of_init()
1802 pr_err("L2C: device tree omits to specify cache-level\n"); in l2x0_of_init()
1805 pr_err("L2C: device tree specifies invalid cache level\n"); in l2x0_of_init()