Lines Matching +full:i +full:- +full:tlb +full:- +full:size
1 # SPDX-License-Identifier: GPL-2.0
17 A 32-bit RISC microprocessor based on the ARM7 processor core
36 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
53 A 32-bit RISC processor with 8KB cache or 4KB variants,
69 A 32-bit RISC microprocessor based on the ARM9 processor core
147 instruction sequences for cache and TLB operations. Curiously,
166 Branch Target Buffer, Unified TLB and cache line size 16.
182 ARM940T is a member of the ARM9TDMI family of general-
184 instruction and 4KB data cases, each with a 4-word line
190 # ARM946E-S
201 ARM946E-S is a member of the ARM9E-S family of high-
202 performance, 32-bit system-on-chip processor solutions.
203 The TCM and ARMv5TE 32-bit instruction set is supported.
205 Say Y if you want support for the ARM946E-S processor.
208 # ARM1020 - needs validating
222 with an addition of a floating-point unit.
227 # ARM1020E - needs validating
255 embedded trace macrocell, and a floating-point unit.
260 # ARM1026EJ-S
272 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
275 Say Y if you want support for the ARM1026EJ-S processor.
291 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
296 Say Y if you want support for the SA-110 processor.
364 Relevant for Feroceon-1850 and early Feroceon-2850.
554 # The copy-page model
570 # This selects the TLB model
574 ARM Architecture Version 4 TLB with writethrough cache.
579 ARM Architecture Version 4 TLB with writeback cache.
584 ARM Architecture Version 4 TLB with writeback cache and invalidate
590 Feroceon TLB (v4wbi with non-outer-cachable page table walks).
595 Faraday ARM FA526 architecture, unified TLB with writeback cache
611 tag TLB and possibly cache entries.
637 and to handle IO-space as a special type of memory by assigning
651 interrupts supported by the NVIC on Cortex-M family.
656 # CPU supports 36-bit I/O
711 Extensions to install hypervisors without run-time firmware
750 bool "Built little-endian kernel"
752 Say Y if you plan on running a kernel in little-endian mode.
757 bool "Build big-endian kernel"
760 Say Y if you plan on running a kernel in big-endian mode.
762 but requires big-endian user space.
764 The only ARMv5 platform with big-endian support is
774 Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
781 Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
795 bool "Disable I-Cache (I-bit)"
802 bool "Workaround for I-Cache line size mismatch between CPU cores"
805 Some big.LITTLE systems have I-Cache line size mismatch between
807 proper I-Cache support on such systems. If unsure, say N.
810 bool "Disable D-Cache (C-bit)"
820 default 0x00002000 # default size for ARM946E-S
823 ARM946E-S case, it can vary from 0KB to 1MB.
824 To support such cache operations, it is efficient to know the size
826 If your SoC is configured to have a different size, define the value
830 bool "Force write through D-cache"
838 bool "Round robin I and D cache replacement algorithm"
841 Say Y here to use the predictable round-robin cache replacement
859 Speculation attacks against some high-performance processors rely
866 This config option will take CPU-specific actions to harden
878 Speculation attacks against some high-performance processors can
887 An SMP system using a pre-ARMv6 processor (there are apparently
951 bool "Enable the Broadcom Brahma-B15 read-ahead cache controller"
955 This option enables the Broadcom Brahma-B15 read-ahead cache
956 controller. If disabled, the read-ahead cache remains off.
1045 not automatically drain. This can cause normal, non-cacheable
1047 to suboptimal I/O performance for drivers using coherent DMA.
1085 Setting ARM L1 cache line size to 64 Bytes.
1090 Setting ARM L1 cache line size to 128 Bytes.
1099 bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K || CPU_V7M) && !CPU_V7
1115 On some of the beefier ARMv7-M machines (with DMA and write
1125 bool "Make rodata strictly non-executable"
1129 If this is set, rodata will be made explicitly non-executable. This
1132 additional section-aligned split of rodata from kernel text so it
1133 can be made explicitly non-executable. This padding may waste memory