Lines Matching +full:core +full:- +full:module

1 # SPDX-License-Identifier: GPL-2.0
52 	bool "Include support for Integrator/IM-PD1"
60 	  The IM-PD1 is an add-on logic module for the Integrator which
62 	  The IM-PD1 can be found on the Integrator/PP2 platform.
65 	bool "Integrator/CM720T core module"
71 	bool "Integrator/CM920T core module"
77 	bool "Integrator/CM922T-XA10 core module"
83 	bool "Integrator/CM926EJ-S core module"
89 	bool "Integrator/CM10200E rev.0 core module"
95 	bool "Integrator/CM10200E core module"
101 	bool "Integrator/CM10220E core module"
107 	bool "Integrator/CM1026EJ-S core module"
113 	bool "Integrator/CM1136JF-S core module"
129 	bool "Integrator/CT926 (ARM926EJ-S) core tile"
135 	bool "Integrator/CTB36 (ARM1136JF-S) core tile"
178 	  the ARM926EJ-S core tile, while on an ARMv6/v7 kernel, at least
179 	  one of the ARM1136, ARM1176, ARM11MPCore or Cortex-A9MPCore
180 	  core tile options should be enabled.
183 	bool "Support ARM1136J(F)-S Tile"
191 	bool "Support ARM1176JZ(F)-S Tile"
198 	bool "Support Multicore Cortex-A9 Tile"
201 	  Enable support for the Cortex-A9MPCore tile fitted to the
206 	bool "Support RealView(R) Platform Baseboard for ARM1176JZF-S"
212 	  ARM1176JZF-S.
215 	bool "Support RealView(R) Platform Baseboard for Cortex(tm)-A8 platform"
219 	  Cortex(tm)-A8.  This platform has an on-board Cortex-A8 and has
220 	  support for PCI-E and Compact Flash.
223 	bool "Support RealView(R) Platform Baseboard Explore for Cortex-A9"
253 	  ARM core and logic (FPGA) tiles on the Versatile Express motherboard,
256 	  - CoreTile Express A5x2 (V2P-CA5s)
257 	  - CoreTile Express A9x4 (V2P-CA9)
258 	  - CoreTile Express A15x2 (V2P-CA15)
259 	  - LogicTile Express 13MG (V2F-2XV6) with A5, A7, A9 or A15 SMMs
261 	  - Versatile Express RTSMs (Models)
270 	bool "Enable A5 and A9 only errata work-arounds"
277 	  based on Cortex-A5 and Cortex-A9 processors. In order to
278 	  build a working kernel, you must also enable relevant core
285 	  The TC2 (A15x2 A7x3) versatile express core tile integrates a logic
287 	  between the dual cluster test-chip and the M3 microcontroller that
298 	  with a TC2 (A15x2 A7x3) big.LITTLE core tile.