Lines Matching full:r0
94 cpu_id r0
102 * r0 is cpu to reset
110 * corrupts r0-r3, r12
113 cmp r0, #0
116 cpu_to_halt_reg r1, r0
124 mov r1, r1, lsl r0
130 cmp r3, r0
144 mov r4, r0
146 mov r0, #TEGRA_FLUSH_CACHE_ALL
148 mov r0, r4
151 add r3, r3, r0
153 mov32 r0, tegra20_tear_down_core
155 sub r0, r0, r1
157 add r0, r0, r1
196 mov32 r0, TEGRA_CLK_RESET_BASE
199 str r1, [r0, #CLK_RESET_SCLK_BURST]
200 str r1, [r0, #CLK_RESET_CCLK_BURST]
202 str r1, [r0, #CLK_RESET_CCLK_DIVIDER]
203 str r1, [r0, #CLK_RESET_SCLK_DIVIDER]
205 pll_enable r1, r0, CLK_RESET_PLLM_BASE, PLLM_STORE_MASK
206 pll_enable r1, r0, CLK_RESET_PLLP_BASE, PLLP_STORE_MASK
207 pll_enable r1, r0, CLK_RESET_PLLC_BASE, PLLC_STORE_MASK
233 str r4, [r0, #CLK_RESET_SCLK_BURST]
235 str r4, [r0, #CLK_RESET_CCLK_BURST]
237 mov32 r0, TEGRA_EMC_BASE
238 ldr r1, [r0, #EMC_CFG]
240 str r1, [r0, #EMC_CFG]
243 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
245 str r1, [r0, #EMC_NOP]
246 str r1, [r0, #EMC_NOP]
248 emc_device_mask r1, r0
251 ldr r2, [r0, #EMC_EMC_STATUS]
256 str r1, [r0, #EMC_REQ_CTRL]
258 mov32 r0, TEGRA_PMC_BASE
259 ldr r0, [r0, #PMC_SCRATCH41]
260 ret r0 @ jump to tegra_resume
285 mov r0, #(1 << 28)
286 str r0, [r5, #CLK_RESET_SCLK_BURST]
287 str r0, [r5, #CLK_RESET_CCLK_BURST]
288 mov r0, #0
289 str r0, [r5, #CLK_RESET_CCLK_DIVIDER]
290 str r0, [r5, #CLK_RESET_SCLK_DIVIDER]
298 store_pll_state r0, r1, r5, CLK_RESET_PLLC_BASE, PLLC_STORE_MASK
299 store_pll_state r0, r1, r5, CLK_RESET_PLLM_BASE, PLLM_STORE_MASK
300 store_pll_state r0, r1, r5, CLK_RESET_PLLP_BASE, PLLP_STORE_MASK
303 ldr r0, [r5, #CLK_RESET_PLLM_BASE]
304 bic r0, r0, #(1 << 30)
305 str r0, [r5, #CLK_RESET_PLLM_BASE]
306 ldr r0, [r5, #CLK_RESET_PLLP_BASE]
307 bic r0, r0, #(1 << 30)
308 str r0, [r5, #CLK_RESET_PLLP_BASE]
309 ldr r0, [r5, #CLK_RESET_PLLC_BASE]
310 bic r0, r0, #(1 << 30)
311 str r0, [r5, #CLK_RESET_PLLC_BASE]
314 mov r0, #0 /* brust policy = 32KHz */
315 str r0, [r5, #CLK_RESET_SCLK_BURST]
329 mov r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT
330 orr r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
333 str r0, [r6, r1]
335 ldr r0, [r6, r1] /* memory barrier */
379 ldr r0, [r2, r5] @ r0 is the addr in the pad_address
381 ldr r1, [r0]
385 str r1, [r0] @ set the save val to the addr
393 ldr r0, [r5, #CLK_RESET_SCLK_BURST]
395 str r0, [r2]