Lines Matching +full:0 +full:x90000010
30 #define SA1100_CS0_PHYS 0x00000000
31 #define SA1100_CS1_PHYS 0x08000000
32 #define SA1100_CS2_PHYS 0x10000000
33 #define SA1100_CS3_PHYS 0x18000000
34 #define SA1100_CS4_PHYS 0x40000000
35 #define SA1100_CS5_PHYS 0x48000000
41 #define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */
47 #define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
48 #define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
49 #define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
50 #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
57 #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
58 (0x20000000 + (Nb)*PCMCIASp)
59 #define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */
60 #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
62 #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
65 #define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */
66 #define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */
67 #define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */
68 #define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */
80 * Ser0UDCCR Serial port 0 Universal Serial Bus (USB) Device
82 * Ser0UDCAR Serial port 0 Universal Serial Bus (USB) Device
84 * Ser0UDCOMP Serial port 0 Universal Serial Bus (USB) Device
87 * Ser0UDCIMP Serial port 0 Universal Serial Bus (USB) Device
90 * Ser0UDCCS0 Serial port 0 Universal Serial Bus (USB) Device
91 * Controller (UDC) Control/Status register end-point 0
93 * Ser0UDCCS1 Serial port 0 Universal Serial Bus (USB) Device
96 * Ser0UDCCS2 Serial port 0 Universal Serial Bus (USB) Device
99 * Ser0UDCD0 Serial port 0 Universal Serial Bus (USB) Device
100 * Controller (UDC) Data register end-point 0
102 * Ser0UDCWC Serial port 0 Universal Serial Bus (USB) Device
103 * Controller (UDC) Write Count register end-point 0
105 * Ser0UDCDR Serial port 0 Universal Serial Bus (USB) Device
107 * Ser0UDCSR Serial port 0 Universal Serial Bus (USB) Device
111 #define Ser0UDCCR __REG(0x80000000) /* Ser. port 0 UDC Control Reg. */
112 #define Ser0UDCAR __REG(0x80000004) /* Ser. port 0 UDC Address Reg. */
113 #define Ser0UDCOMP __REG(0x80000008) /* Ser. port 0 UDC Output Maximum Packet size reg. */
114 #define Ser0UDCIMP __REG(0x8000000C) /* Ser. port 0 UDC Input Maximum Packet size reg. */
115 #define Ser0UDCCS0 __REG(0x80000010) /* Ser. port 0 UDC Control/Status reg. end-point 0 */
116 #define Ser0UDCCS1 __REG(0x80000014) /* Ser. port 0 UDC Control/Status reg. end-point 1 (output) */
117 #define Ser0UDCCS2 __REG(0x80000018) /* Ser. port 0 UDC Control/Status reg. end-point 2 (input) */
118 #define Ser0UDCD0 __REG(0x8000001C) /* Ser. port 0 UDC Data reg. end-point 0 */
119 #define Ser0UDCWC __REG(0x80000020) /* Ser. port 0 UDC Write Count reg. end-point 0 */
120 #define Ser0UDCDR __REG(0x80000028) /* Ser. port 0 UDC Data Reg. */
121 #define Ser0UDCSR __REG(0x80000030) /* Ser. port 0 UDC Status Reg. */
123 #define UDCCR_UDD 0x00000001 /* UDC Disable */
124 #define UDCCR_UDA 0x00000002 /* UDC Active (read) */
125 #define UDCCR_RESIM 0x00000004 /* Resume Interrupt Mask, per errata */
126 #define UDCCR_EIM 0x00000008 /* End-point 0 Interrupt Mask */
128 #define UDCCR_RIM 0x00000010 /* Receive Interrupt Mask */
130 #define UDCCR_TIM 0x00000020 /* Transmit Interrupt Mask */
132 #define UDCCR_SRM 0x00000040 /* Suspend/Resume interrupt Mask */
135 #define UDCCR_REM 0x00000080 /* REset interrupt Mask (disable) */
137 #define UDCAR_ADD Fld (7, 0) /* function ADDress */
139 #define UDCOMP_OUTMAXP Fld (8, 0) /* OUTput MAXimum Packet size - 1 */
145 #define UDCIMP_INMAXP Fld (8, 0) /* INput MAXimum Packet size - 1 */
151 #define UDCCS0_OPR 0x00000001 /* Output Packet Ready (read) */
152 #define UDCCS0_IPR 0x00000002 /* Input Packet Ready */
153 #define UDCCS0_SST 0x00000004 /* Sent STall */
154 #define UDCCS0_FST 0x00000008 /* Force STall */
155 #define UDCCS0_DE 0x00000010 /* Data End */
156 #define UDCCS0_SE 0x00000020 /* Setup End (read) */
157 #define UDCCS0_SO 0x00000040 /* Serviced Output packet ready */
159 #define UDCCS0_SSE 0x00000080 /* Serviced Setup End (write) */
161 #define UDCCS1_RFS 0x00000001 /* Receive FIFO 12-bytes or more */
163 #define UDCCS1_RPC 0x00000002 /* Receive Packet Complete */
164 #define UDCCS1_RPE 0x00000004 /* Receive Packet Error (read) */
165 #define UDCCS1_SST 0x00000008 /* Sent STall */
166 #define UDCCS1_FST 0x00000010 /* Force STall */
167 #define UDCCS1_RNE 0x00000020 /* Receive FIFO Not Empty (read) */
169 #define UDCCS2_TFS 0x00000001 /* Transmit FIFO 8-bytes or less */
171 #define UDCCS2_TPC 0x00000002 /* Transmit Packet Complete */
172 #define UDCCS2_TPE 0x00000004 /* Transmit Packet Error (read) */
173 #define UDCCS2_TUR 0x00000008 /* Transmit FIFO Under-Run */
174 #define UDCCS2_SST 0x00000010 /* Sent STall */
175 #define UDCCS2_FST 0x00000020 /* Force STall */
177 #define UDCD0_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
179 #define UDCWC_WC Fld (4, 0) /* Write Count */
181 #define UDCDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
183 #define UDCSR_EIR 0x00000001 /* End-point 0 Interrupt Request */
184 #define UDCSR_RIR 0x00000002 /* Receive Interrupt Request */
185 #define UDCSR_TIR 0x00000004 /* Transmit Interrupt Request */
186 #define UDCSR_SUSIR 0x00000008 /* SUSpend Interrupt Request */
187 #define UDCSR_RESIR 0x00000010 /* RESume Interrupt Request */
188 #define UDCSR_RSTIR 0x00000020 /* ReSeT Interrupt Request */
196 * Receiver/Transmitter (UART) Control Register 0
211 * Receiver/Transmitter (UART) Status Register 0
217 * Receiver/Transmitter (UART) Control Register 0
235 * Receiver/Transmitter (UART) Status Register 0
241 * Receiver/Transmitter (UART) Control Register 0
256 * Receiver/Transmitter (UART) Status Register 0
267 #define _UTCR0(Nb) __REG(0x80010000 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 0 [1..3] */
268 #define _UTCR1(Nb) __REG(0x80010004 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 1 [1..3] */
269 #define _UTCR2(Nb) __REG(0x80010008 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 2 [1..3] */
270 #define _UTCR3(Nb) __REG(0x8001000C + ((Nb) - 1)*0x00020000) /* UART Control Reg. 3 [1..3] */
271 #define _UTCR4(Nb) __REG(0x80010010 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 4 [2] */
272 #define _UTDR(Nb) __REG(0x80010014 + ((Nb) - 1)*0x00020000) /* UART Data Reg. [1..3] */
273 #define _UTSR0(Nb) __REG(0x8001001C + ((Nb) - 1)*0x00020000) /* UART Status Reg. 0 [1..3] */
274 #define _UTSR1(Nb) __REG(0x80010020 + ((Nb) - 1)*0x00020000) /* UART Status Reg. 1 [1..3] */
276 #define Ser1UTCR0 _UTCR0 (1) /* Ser. port 1 UART Control Reg. 0 */
281 #define Ser1UTSR0 _UTSR0 (1) /* Ser. port 1 UART Status Reg. 0 */
284 #define Ser2UTCR0 _UTCR0 (2) /* Ser. port 2 UART Control Reg. 0 */
290 #define Ser2UTSR0 _UTSR0 (2) /* Ser. port 2 UART Status Reg. 0 */
293 #define Ser3UTCR0 _UTCR0 (3) /* Ser. port 3 UART Control Reg. 0 */
298 #define Ser3UTSR0 _UTSR0 (3) /* Ser. port 3 UART Status Reg. 0 */
307 #define UTCR0 0x00
308 #define UTCR1 0x04
309 #define UTCR2 0x08
310 #define UTCR3 0x0c
311 #define UTDR 0x14
312 #define UTSR0 0x1c
313 #define UTSR1 0x20
315 #define UTCR0_PE 0x00000001 /* Parity Enable */
316 #define UTCR0_OES 0x00000002 /* Odd/Even parity Select */
317 #define UTCR0_OddPar (UTCR0_OES*0) /* Odd Parity */
319 #define UTCR0_SBS 0x00000004 /* Stop Bit Select */
320 #define UTCR0_1StpBit (UTCR0_SBS*0) /* 1 Stop Bit per frame */
322 #define UTCR0_DSS 0x00000008 /* Data Size Select */
323 #define UTCR0_7BitData (UTCR0_DSS*0) /* 7-Bit Data */
325 #define UTCR0_SCE 0x00000010 /* Sample Clock Enable */
328 #define UTCR0_RCE 0x00000020 /* Receive Clock Edge select */
329 #define UTCR0_RcRsEdg (UTCR0_RCE*0) /* Receive clock Rising-Edge */
331 #define UTCR0_TCE 0x00000040 /* Transmit Clock Edge select */
332 #define UTCR0_TrRsEdg (UTCR0_TCE*0) /* Transmit clock Rising-Edge */
337 #define UTCR1_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */
338 #define UTCR2_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */
339 /* fua = fxtl/(16*(BRD[11:0] + 1)) */
340 /* Tua = 16*(BRD [11:0] + 1)*Txtl */
358 #define UTCR3_RXE 0x00000001 /* Receive Enable */
359 #define UTCR3_TXE 0x00000002 /* Transmit Enable */
360 #define UTCR3_BRK 0x00000004 /* BReaK mode */
361 #define UTCR3_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */
363 #define UTCR3_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */
365 #define UTCR3_LBM 0x00000020 /* Look-Back Mode */
370 #define UTCR4_HSE 0x00000001 /* Hewlett-Packard Serial InfraRed */
372 #define UTCR4_NRZ (UTCR4_HSE*0) /* Non-Return to Zero modulation */
374 #define UTCR4_LPM 0x00000002 /* Low-Power Mode */
375 #define UTCR4_Z3_16Bit (UTCR4_LPM*0) /* Zero pulse = 3/16 Bit time */
378 #define UTDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
379 #if 0 /* Hidden receive FIFO bits */
380 #define UTDR_PRE 0x00000100 /* receive PaRity Error (read) */
381 #define UTDR_FRE 0x00000200 /* receive FRaming Error (read) */
382 #define UTDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
383 #endif /* 0 */
385 #define UTSR0_TFS 0x00000001 /* Transmit FIFO 1/2-full or less */
387 #define UTSR0_RFS 0x00000002 /* Receive FIFO 1/3-to-2/3-full or */
389 #define UTSR0_RID 0x00000004 /* Receiver IDle */
390 #define UTSR0_RBB 0x00000008 /* Receive Beginning of Break */
391 #define UTSR0_REB 0x00000010 /* Receive End of Break */
392 #define UTSR0_EIF 0x00000020 /* Error In FIFO (read) */
394 #define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */
395 #define UTSR1_RNE 0x00000002 /* Receive FIFO Not Empty (read) */
396 #define UTSR1_TNF 0x00000004 /* Transmit FIFO Not Full (read) */
397 #define UTSR1_PRE 0x00000008 /* receive PaRity Error (read) */
398 #define UTSR1_FRE 0x00000010 /* receive FRaming Error (read) */
399 #define UTSR1_ROR 0x00000020 /* Receive FIFO Over-Run (read) */
407 * Control Register 0 (read/write).
419 * Status Register 0 (read/write).
429 #define Ser1SDCR0 __REG(0x80020060) /* Ser. port 1 SDLC Control Reg. 0 */
430 #define Ser1SDCR1 __REG(0x80020064) /* Ser. port 1 SDLC Control Reg. 1 */
431 #define Ser1SDCR2 __REG(0x80020068) /* Ser. port 1 SDLC Control Reg. 2 */
432 #define Ser1SDCR3 __REG(0x8002006C) /* Ser. port 1 SDLC Control Reg. 3 */
433 #define Ser1SDCR4 __REG(0x80020070) /* Ser. port 1 SDLC Control Reg. 4 */
434 #define Ser1SDDR __REG(0x80020078) /* Ser. port 1 SDLC Data Reg. */
435 #define Ser1SDSR0 __REG(0x80020080) /* Ser. port 1 SDLC Status Reg. 0 */
436 #define Ser1SDSR1 __REG(0x80020084) /* Ser. port 1 SDLC Status Reg. 1 */
438 #define SDCR0_SUS 0x00000001 /* SDLC/UART Select */
439 #define SDCR0_SDLC (SDCR0_SUS*0) /* SDLC mode (TXD1 & RXD1) */
441 #define SDCR0_SDF 0x00000002 /* Single/Double start Flag select */
442 #define SDCR0_SglFlg (SDCR0_SDF*0) /* Single start Flag */
444 #define SDCR0_LBM 0x00000004 /* Look-Back Mode */
445 #define SDCR0_BMS 0x00000008 /* Bit Modulation Select */
446 #define SDCR0_FM0 (SDCR0_BMS*0) /* Freq. Modulation zero (0) */
448 #define SDCR0_SCE 0x00000010 /* Sample Clock Enable (GPIO [16]) */
449 #define SDCR0_SCD 0x00000020 /* Sample Clock Direction select */
451 #define SDCR0_SClkIn (SDCR0_SCD*0) /* Sample Clock Input */
453 #define SDCR0_RCE 0x00000040 /* Receive Clock Edge select */
454 #define SDCR0_RcRsEdg (SDCR0_RCE*0) /* Receive clock Rising-Edge */
456 #define SDCR0_TCE 0x00000080 /* Transmit Clock Edge select */
457 #define SDCR0_TrRsEdg (SDCR0_TCE*0) /* Transmit clock Rising-Edge */
460 #define SDCR1_AAF 0x00000001 /* Abort After Frame enable */
462 #define SDCR1_TXE 0x00000002 /* Transmit Enable */
463 #define SDCR1_RXE 0x00000004 /* Receive Enable */
464 #define SDCR1_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */
466 #define SDCR1_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */
468 #define SDCR1_AME 0x00000020 /* Address Match Enable */
469 #define SDCR1_TUS 0x00000040 /* Transmit FIFO Under-run Select */
470 #define SDCR1_EFrmURn (SDCR1_TUS*0) /* End Frame on Under-Run */
472 #define SDCR1_RAE 0x00000080 /* Receive Abort interrupt Enable */
474 #define SDCR2_AMV Fld (8, 0) /* Address Match Value */
476 #define SDCR3_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */
477 #define SDCR4_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */
478 /* fsd = fxtl/(16*(BRD[11:0] + 1)) */
479 /* Tsd = 16*(BRD[11:0] + 1)*Txtl */
497 #define SDDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
498 #if 0 /* Hidden receive FIFO bits */
499 #define SDDR_EOF 0x00000100 /* receive End-Of-Frame (read) */
500 #define SDDR_CRE 0x00000200 /* receive CRC Error (read) */
501 #define SDDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
502 #endif /* 0 */
504 #define SDSR0_EIF 0x00000001 /* Error In FIFO (read) */
505 #define SDSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */
506 #define SDSR0_RAB 0x00000004 /* Receive ABort */
507 #define SDSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */
509 #define SDSR0_RFS 0x00000010 /* Receive FIFO 1/3-to-2/3-full or */
512 #define SDSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */
513 #define SDSR1_TBY 0x00000002 /* Transmitter BusY (read) */
514 #define SDSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
515 #define SDSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */
516 #define SDSR1_RTD 0x00000010 /* Receive Transition Detected */
517 #define SDSR1_EOF 0x00000020 /* receive End-Of-Frame (read) */
518 #define SDSR1_CRE 0x00000040 /* receive CRC Error (read) */
519 #define SDSR1_ROR 0x00000080 /* Receive FIFO Over-Run (read) */
527 * controller (HSSP) Control Register 0 (read/write).
533 * controller (HSSP) Status Register 0 (read/write).
543 #define Ser2HSCR0 __REG(0x80040060) /* Ser. port 2 HSSP Control Reg. 0 */
544 #define Ser2HSCR1 __REG(0x80040064) /* Ser. port 2 HSSP Control Reg. 1 */
545 #define Ser2HSDR __REG(0x8004006C) /* Ser. port 2 HSSP Data Reg. */
546 #define Ser2HSSR0 __REG(0x80040074) /* Ser. port 2 HSSP Status Reg. 0 */
547 #define Ser2HSSR1 __REG(0x80040078) /* Ser. port 2 HSSP Status Reg. 1 */
548 #define Ser2HSCR2 __REG(0x90060028) /* Ser. port 2 HSSP Control Reg. 2 */
550 #define HSCR0_ITR 0x00000001 /* IrDA Transmission Rate */
551 #define HSCR0_UART (HSCR0_ITR*0) /* UART mode (115.2 kb/s if IrDA) */
553 #define HSCR0_LBM 0x00000002 /* Look-Back Mode */
554 #define HSCR0_TUS 0x00000004 /* Transmit FIFO Under-run Select */
555 #define HSCR0_EFrmURn (HSCR0_TUS*0) /* End Frame on Under-Run */
557 #define HSCR0_TXE 0x00000008 /* Transmit Enable */
558 #define HSCR0_RXE 0x00000010 /* Receive Enable */
559 #define HSCR0_RIE 0x00000020 /* Receive FIFO 2/5-to-3/5-full or */
561 #define HSCR0_TIE 0x00000040 /* Transmit FIFO 1/2-full or less */
563 #define HSCR0_AME 0x00000080 /* Address Match Enable */
565 #define HSCR1_AMV Fld (8, 0) /* Address Match Value */
567 #define HSDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
568 #if 0 /* Hidden receive FIFO bits */
569 #define HSDR_EOF 0x00000100 /* receive End-Of-Frame (read) */
570 #define HSDR_CRE 0x00000200 /* receive CRC Error (read) */
571 #define HSDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
572 #endif /* 0 */
574 #define HSSR0_EIF 0x00000001 /* Error In FIFO (read) */
575 #define HSSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */
576 #define HSSR0_RAB 0x00000004 /* Receive ABort */
577 #define HSSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */
579 #define HSSR0_RFS 0x00000010 /* Receive FIFO 2/5-to-3/5-full or */
581 #define HSSR0_FRE 0x00000020 /* receive FRaming Error */
583 #define HSSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */
584 #define HSSR1_TBY 0x00000002 /* Transmitter BusY (read) */
585 #define HSSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
586 #define HSSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */
587 #define HSSR1_EOF 0x00000010 /* receive End-Of-Frame (read) */
588 #define HSSR1_CRE 0x00000020 /* receive CRC Error (read) */
589 #define HSSR1_ROR 0x00000040 /* Receive FIFO Over-Run (read) */
591 #define HSCR2_TXP 0x00040000 /* Transmit data Polarity (TXD_2) */
592 #define HSCR2_TrDataL (HSCR2_TXP*0) /* Transmit Data active Low */
596 #define HSCR2_RXP 0x00080000 /* Receive data Polarity (RXD_2) */
597 #define HSCR2_RcDataL (HSCR2_RXP*0) /* Receive Data active Low */
608 * Control Register 0 (read/write).
610 * Data Register 0 (audio, read/write).
630 #define Ser4MCCR0 __REG(0x80060000) /* Ser. port 4 MCP Control Reg. 0 */
631 #define Ser4MCDR0 __REG(0x80060008) /* Ser. port 4 MCP Data Reg. 0 (audio) */
632 #define Ser4MCDR1 __REG(0x8006000C) /* Ser. port 4 MCP Data Reg. 1 (telecom) */
633 #define Ser4MCDR2 __REG(0x80060010) /* Ser. port 4 MCP Data Reg. 2 (CODEC reg.) */
634 #define Ser4MCSR __REG(0x80060018) /* Ser. port 4 MCP Status Reg. */
635 #define Ser4MCCR1 __REG(0x90060030) /* Ser. port 4 MCP Control Reg. 1 */
637 #define MCCR0_ASD Fld (7, 0) /* Audio Sampling rate Divisor/32 */
663 #define MCCR0_MCE 0x00010000 /* MCP Enable */
664 #define MCCR0_ECS 0x00020000 /* External Clock Select */
665 #define MCCR0_IntClk (MCCR0_ECS*0) /* Internal Clock (10 or 12 MHz) */
667 #define MCCR0_ADM 0x00040000 /* A/D (audio/telecom) data */
669 #define MCCR0_VldBit (MCCR0_ADM*0) /* Valid Bit storing mode */
671 #define MCCR0_TTE 0x00080000 /* Telecom Transmit FIFO 1/2-full */
673 #define MCCR0_TRE 0x00100000 /* Telecom Receive FIFO 1/2-full */
675 #define MCCR0_ATE 0x00200000 /* Audio Transmit FIFO 1/2-full */
677 #define MCCR0_ARE 0x00400000 /* Audio Receive FIFO 1/2-full or */
679 #define MCCR0_LBM 0x00800000 /* Look-Back Mode */
692 #define MCDR2_DATA Fld (16, 0) /* reg. DATA */
693 #define MCDR2_RW 0x00010000 /* reg. Read/Write (transmit) */
694 #define MCDR2_Rd (MCDR2_RW*0) /* reg. Read */
698 #define MCSR_ATS 0x00000001 /* Audio Transmit FIFO 1/2-full */
700 #define MCSR_ARS 0x00000002 /* Audio Receive FIFO 1/2-full or */
702 #define MCSR_TTS 0x00000004 /* Telecom Transmit FIFO 1/2-full */
704 #define MCSR_TRS 0x00000008 /* Telecom Receive FIFO 1/2-full */
706 #define MCSR_ATU 0x00000010 /* Audio Transmit FIFO Under-run */
707 #define MCSR_ARO 0x00000020 /* Audio Receive FIFO Over-run */
708 #define MCSR_TTU 0x00000040 /* Telecom Transmit FIFO Under-run */
709 #define MCSR_TRO 0x00000080 /* Telecom Receive FIFO Over-run */
710 #define MCSR_ANF 0x00000100 /* Audio transmit FIFO Not Full */
712 #define MCSR_ANE 0x00000200 /* Audio receive FIFO Not Empty */
714 #define MCSR_TNF 0x00000400 /* Telecom transmit FIFO Not Full */
716 #define MCSR_TNE 0x00000800 /* Telecom receive FIFO Not Empty */
718 #define MCSR_CWC 0x00001000 /* CODEC register Write Completed */
720 #define MCSR_CRC 0x00002000 /* CODEC register Read Completed */
722 #define MCSR_ACE 0x00004000 /* Audio CODEC Enabled (read) */
723 #define MCSR_TCE 0x00008000 /* Telecom CODEC Enabled (read) */
725 #define MCCR1_CFS 0x00100000 /* Clock Freq. Select */
726 #define MCCR1_F12MHz (MCCR1_CFS*0) /* Freq. (fmc) = ~ 12 MHz */
737 * Register 0 (read/write).
753 #define Ser4SSCR0 __REG(0x80070060) /* Ser. port 4 SSP Control Reg. 0 */
754 #define Ser4SSCR1 __REG(0x80070064) /* Ser. port 4 SSP Control Reg. 1 */
755 #define Ser4SSDR __REG(0x8007006C) /* Ser. port 4 SSP Data Reg. */
756 #define Ser4SSSR __REG(0x80070074) /* Ser. port 4 SSP Status Reg. */
758 #define SSCR0_DSS Fld (4, 0) /* Data Size - 1 Select [3..15] */
764 (0 << FShft (SSCR0_FRF))
770 #define SSCR0_SSE 0x00000080 /* SSP Enable */
783 #define SSCR1_RIE 0x00000001 /* Receive FIFO 1/2-full or more */
785 #define SSCR1_TIE 0x00000002 /* Transmit FIFO 1/2-full or less */
787 #define SSCR1_LBM 0x00000004 /* Look-Back Mode */
788 #define SSCR1_SPO 0x00000008 /* Sample clock (SCLK) POlarity */
789 #define SSCR1_SClkIactL (SSCR1_SPO*0) /* Sample Clock Inactive Low */
791 #define SSCR1_SP 0x00000010 /* Sample clock (SCLK) Phase */
792 #define SSCR1_SClk1P (SSCR1_SP*0) /* Sample Clock active 1 Period */
796 #define SSCR1_ECS 0x00000020 /* External Clock Select */
797 #define SSCR1_IntClk (SSCR1_ECS*0) /* Internal Clock */
800 #define SSDR_DATA Fld (16, 0) /* receive/transmit DATA FIFOs */
802 #define SSSR_TNF 0x00000002 /* Transmit FIFO Not Full (read) */
803 #define SSSR_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
804 #define SSSR_BSY 0x00000008 /* SSP BuSY (read) */
805 #define SSSR_TFS 0x00000010 /* Transmit FIFO 1/2-full or less */
807 #define SSSR_RFS 0x00000020 /* Receive FIFO 1/2-full or more */
809 #define SSSR_ROR 0x00000040 /* Receive FIFO Over-Run */
816 * OSMR0 Operating System (OS) timer Match Register 0
834 #define OSMR0 io_p2v(0x90000000) /* OS timer Match Reg. 0 */
835 #define OSMR1 io_p2v(0x90000004) /* OS timer Match Reg. 1 */
836 #define OSMR2 io_p2v(0x90000008) /* OS timer Match Reg. 2 */
837 #define OSMR3 io_p2v(0x9000000c) /* OS timer Match Reg. 3 */
838 #define OSCR io_p2v(0x90000010) /* OS timer Counter Reg. */
839 #define OSSR io_p2v(0x90000014) /* OS timer Status Reg. */
840 #define OWER io_p2v(0x90000018) /* OS timer Watch-dog Enable Reg. */
841 #define OIER io_p2v(0x9000001C) /* OS timer Interrupt Enable Reg. */
843 #define OSSR_M(Nb) /* Match detected [0..3] */ \
844 (0x00000001 << (Nb))
845 #define OSSR_M0 OSSR_M (0) /* Match detected 0 */
850 #define OWER_WME 0x00000001 /* Watch-dog Match Enable */
853 #define OIER_E(Nb) /* match interrupt Enable [0..3] */ \
854 (0x00000001 << (Nb))
855 #define OIER_E0 OIER_E (0) /* match interrupt Enable 0 */
884 #define PMCR __REG(0x90020000) /* PM Control Reg. */
885 #define PSSR __REG(0x90020004) /* PM Sleep Status Reg. */
886 #define PSPR __REG(0x90020008) /* PM Scratch-Pad Reg. */
887 #define PWER __REG(0x9002000C) /* PM Wake-up Enable Reg. */
888 #define PCFR __REG(0x90020010) /* PM general ConFiguration Reg. */
889 #define PPCR __REG(0x90020014) /* PM PLL Configuration Reg. */
890 #define PGSR __REG(0x90020018) /* PM GPIO Sleep state Reg. */
891 #define POSR __REG(0x9002001C) /* PM Oscillator Status Reg. */
893 #define PMCR_SF 0x00000001 /* Sleep Force (set only) */
895 #define PSSR_SS 0x00000001 /* Software Sleep */
896 #define PSSR_BFS 0x00000002 /* Battery Fault Status */
898 #define PSSR_VFS 0x00000004 /* Vdd Fault Status (VDD_FAULT) */
899 #define PSSR_DH 0x00000008 /* DRAM control Hold */
900 #define PSSR_PH 0x00000010 /* Peripheral control Hold */
902 #define PWER_GPIO(Nb) GPIO_GPIO (Nb) /* GPIO [0..27] wake-up enable */
903 #define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */
931 #define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
933 #define PCFR_OPDE 0x00000001 /* Oscillator Power-Down Enable */
934 #define PCFR_ClkRun (PCFR_OPDE*0) /* Clock Running in sleep mode */
936 #define PCFR_FP 0x00000002 /* Float PCMCIA pins */
937 #define PCFR_PCMCIANeg (PCFR_FP*0) /* PCMCIA pins Negated (1) */
939 #define PCFR_FS 0x00000004 /* Float Static memory pins */
940 #define PCFR_StMemNeg (PCFR_FS*0) /* Static Memory pins Negated (1) */
942 #define PCFR_FO 0x00000008 /* Force RTC oscillator */
945 #define PPCR_CCF Fld (5, 0) /* CPU core Clock (CCLK) Freq. */
947 (0x00 << FShft (PPCR_CCF))
949 (0x01 << FShft (PPCR_CCF))
951 (0x02 << FShft (PPCR_CCF))
953 (0x03 << FShft (PPCR_CCF))
955 (0x04 << FShft (PPCR_CCF))
957 (0x05 << FShft (PPCR_CCF))
959 (0x06 << FShft (PPCR_CCF))
961 (0x07 << FShft (PPCR_CCF))
963 (0x08 << FShft (PPCR_CCF))
965 (0x09 << FShft (PPCR_CCF))
967 (0x0A << FShft (PPCR_CCF))
969 (0x0B << FShft (PPCR_CCF))
971 (0x0C << FShft (PPCR_CCF))
973 (0x0D << FShft (PPCR_CCF))
975 (0x0E << FShft (PPCR_CCF))
977 (0x0F << FShft (PPCR_CCF))
1013 #define POSR_OOK 0x00000001 /* RTC Oscillator (32.768 kHz) OK */
1025 #define RSRR __REG(0x90030000) /* RC Software Reset Reg. */
1026 #define RCSR __REG(0x90030004) /* RC Status Reg. */
1028 #define RSRR_SWR 0x00000001 /* SoftWare Reset (set only) */
1030 #define RCSR_HWR 0x00000001 /* HardWare Reset */
1031 #define RCSR_SWR 0x00000002 /* SoftWare Reset */
1032 #define RCSR_WDR 0x00000004 /* Watch-Dog Reset */
1033 #define RCSR_SMR 0x00000008 /* Sleep-Mode Reset */
1043 #define TUCR __REG(0x90030008) /* Test Unit Control Reg. */
1045 #define TUCR_TIC 0x00000040 /* TIC mode */
1046 #define TUCR_TTST 0x00000080 /* Trim TeST mode */
1047 #define TUCR_RCRC 0x00000100 /* Richard's Cyclic Redundancy */
1049 #define TUCR_PMD 0x00000200 /* Power Management Disable */
1050 #define TUCR_MR 0x00000400 /* Memory Request mode */
1051 #define TUCR_NoMB (TUCR_MR*0) /* No Memory Bus request & grant */
1055 #define TUCR_FDC 0x00800000 /* RTC Force Delete Count */
1056 #define TUCR_FMC 0x01000000 /* Force Michelle's Control mode */
1057 #define TUCR_TMC 0x02000000 /* RTC Trimmer Multiplexer Control */
1058 #define TUCR_DPS 0x04000000 /* Disallow Pad Sleep */
1061 (0 << FShft (TUCR_TSEL))
1105 #define GPLR __REG(0x90040000) /* GPIO Pin Level Reg. */
1106 #define GPDR __REG(0x90040004) /* GPIO Pin Direction Reg. */
1107 #define GPSR __REG(0x90040008) /* GPIO Pin output Set Reg. */
1108 #define GPCR __REG(0x9004000C) /* GPIO Pin output Clear Reg. */
1109 #define GRER __REG(0x90040010) /* GPIO Rising-Edge detect Reg. */
1110 #define GFER __REG(0x90040014) /* GPIO Falling-Edge detect Reg. */
1111 #define GEDR __REG(0x90040018) /* GPIO Edge Detect status Reg. */
1112 #define GAFR __REG(0x9004001C) /* GPIO Alternate Function Reg. */
1114 #define GPIO_MIN (0)
1117 #define GPIO_GPIO(Nb) /* GPIO [0..27] */ \
1118 (0x00000001 << (Nb))
1119 #define GPIO_GPIO0 GPIO_GPIO (0) /* GPIO [0] */
1185 #define GPDR_In 0 /* Input */
1210 #define ICIP __REG(0x90050000) /* IC IRQ Pending reg. */
1211 #define ICMR __REG(0x90050004) /* IC Mask Reg. */
1212 #define ICLR __REG(0x90050008) /* IC Level Reg. */
1213 #define ICCR __REG(0x9005000C) /* IC Control Reg. */
1214 #define ICFP __REG(0x90050010) /* IC FIQ Pending reg. */
1215 #define ICPR __REG(0x90050020) /* IC Pending Reg. */
1217 #define IC_GPIO(Nb) /* GPIO [0..10] */ \
1218 (0x00000001 << (Nb))
1219 #define IC_GPIO0 IC_GPIO (0) /* GPIO [0] */
1230 #define IC_GPIO11_27 0x00000800 /* GPIO [11:27] (ORed) */
1231 #define IC_LCD 0x00001000 /* LCD controller */
1232 #define IC_Ser0UDC 0x00002000 /* Ser. port 0 UDC */
1233 #define IC_Ser1SDLC 0x00004000 /* Ser. port 1 SDLC */
1234 #define IC_Ser1UART 0x00008000 /* Ser. port 1 UART */
1235 #define IC_Ser2ICP 0x00010000 /* Ser. port 2 ICP */
1236 #define IC_Ser3UART 0x00020000 /* Ser. port 3 UART */
1237 #define IC_Ser4MCP 0x00040000 /* Ser. port 4 MCP */
1238 #define IC_Ser4SSP 0x00080000 /* Ser. port 4 SSP */
1239 #define IC_DMA(Nb) /* DMA controller channel [0..5] */ \
1240 (0x00100000 << (Nb))
1241 #define IC_DMA0 IC_DMA (0) /* DMA controller channel 0 */
1247 #define IC_OST(Nb) /* OS Timer match [0..3] */ \
1248 (0x04000000 << (Nb))
1249 #define IC_OST0 IC_OST (0) /* OS Timer match 0 */
1253 #define IC_RTC1Hz 0x40000000 /* RTC 1 Hz clock */
1254 #define IC_RTCAlrm 0x80000000 /* RTC Alarm */
1256 #define ICLR_IRQ 0 /* Interrupt ReQuest */
1259 #define ICCR_DIM 0x00000001 /* Disable Idle-mode interrupt */
1261 #define ICCR_IdleAllInt (ICCR_DIM*0) /* Idle-mode All Interrupt enable */
1283 #define PPDR __REG(0x90060000) /* PPC Pin Direction Reg. */
1284 #define PPSR __REG(0x90060004) /* PPC Pin State Reg. */
1285 #define PPAR __REG(0x90060008) /* PPC Pin Assignment Reg. */
1286 #define PSDR __REG(0x9006000C) /* PPC Sleep-mode pin Direction Reg. */
1287 #define PPFR __REG(0x90060010) /* PPC Pin Flag Reg. */
1289 #define PPC_LDD(Nb) /* LCD Data [0..7] */ \
1290 (0x00000001 << (Nb))
1291 #define PPC_LDD0 PPC_LDD (0) /* LCD Data [0] */
1299 #define PPC_L_PCLK 0x00000100 /* LCD Pixel CLocK */
1300 #define PPC_L_LCLK 0x00000200 /* LCD Line CLocK */
1301 #define PPC_L_FCLK 0x00000400 /* LCD Frame CLocK */
1302 #define PPC_L_BIAS 0x00000800 /* LCD AC BIAS */
1304 #define PPC_TXD1 0x00001000 /* SDLC/UART Transmit Data 1 */
1305 #define PPC_RXD1 0x00002000 /* SDLC/UART Receive Data 1 */
1307 #define PPC_TXD2 0x00004000 /* IPC Transmit Data 2 */
1308 #define PPC_RXD2 0x00008000 /* IPC Receive Data 2 */
1310 #define PPC_TXD3 0x00010000 /* UART Transmit Data 3 */
1311 #define PPC_RXD3 0x00020000 /* UART Receive Data 3 */
1313 #define PPC_TXD4 0x00040000 /* MCP/SSP Transmit Data 4 */
1314 #define PPC_RXD4 0x00080000 /* MCP/SSP Receive Data 4 */
1315 #define PPC_SCLK 0x00100000 /* MCP/SSP Sample CLocK */
1316 #define PPC_SFRM 0x00200000 /* MCP/SSP Sample FRaMe */
1318 #define PPDR_In 0 /* Input */
1322 #define PPAR_UPR 0x00001000 /* UART Pin Reassignment */
1323 #define PPAR_UARTTR (PPAR_UPR*0) /* UART on TXD_1 & RXD_1 */
1326 #define PPAR_SPR 0x00040000 /* SSP Pin Reassignment */
1327 #define PPAR_SSPTRSS (PPAR_SPR*0) /* SSP on TXD_C, RXD_C, SCLK_C, */
1331 #define PSDR_OutL 0 /* Output Low in sleep mode */
1334 #define PPFR_LCD 0x00000001 /* LCD controller */
1335 #define PPFR_SP1TX 0x00001000 /* Ser. Port 1 SDLC/UART Transmit */
1336 #define PPFR_SP1RX 0x00002000 /* Ser. Port 1 SDLC/UART Receive */
1337 #define PPFR_SP2TX 0x00004000 /* Ser. Port 2 ICP Transmit */
1338 #define PPFR_SP2RX 0x00008000 /* Ser. Port 2 ICP Receive */
1339 #define PPFR_SP3TX 0x00010000 /* Ser. Port 3 UART Transmit */
1340 #define PPFR_SP3RX 0x00020000 /* Ser. Port 3 UART Receive */
1341 #define PPFR_SP4 0x00040000 /* Ser. Port 4 MCP/SSP */
1342 #define PPFR_PerEn 0 /* Peripheral Enabled */
1353 * Column Address Strobe (CAS) shift register 0
1368 #define MDCNFG __REG(0xA0000000) /* DRAM CoNFiGuration reg. */
1369 #define MDCAS0 __REG(0xA0000004) /* DRAM CAS shift reg. 0 */
1370 #define MDCAS1 __REG(0xA0000008) /* DRAM CAS shift reg. 1 */
1371 #define MDCAS2 __REG(0xA000000c) /* DRAM CAS shift reg. 2 */
1374 #define MDCNFG_DE(Nb) /* DRAM Enable bank [0..3] */ \
1375 (0x00000001 << (Nb))
1376 #define MDCNFG_DE0 MDCNFG_DE (0) /* DRAM Enable bank 0 */
1383 #define MDCNFG_CDB2 0x00000040 /* shift reg. Clock Divide By 2 */
1396 #define MDCNFG_DataLtch(Tcpu) /* Data Latch delay [0..3 Tcpu] */ \
1401 /* [0..262136 Tcpu] */ \
1405 #define MDCNFG_SA1110_DE0 0x00000001 /* DRAM Enable bank 0 */
1406 #define MDCNFG_SA1110_DE1 0x00000002 /* DRAM Enable bank 1 */
1407 #define MDCNFG_SA1110_DTIM0 0x00000004 /* DRAM timing type 0/1 */
1408 #define MDCNFG_SA1110_DWID0 0x00000008 /* DRAM bus width 0/1 */
1410 /* bank 0/1 */
1411 #define MDCNFG_SA1110_CDB20 0x00000080 /* Mem Clock divide by 2 0/1 */
1412 #define MDCNFG_SA1110_TRP0 Fld(3, 8) /* RAS precharge 0/1 */
1414 /* deassertion 0/1 */
1415 #define MDCNFG_SA1110_TWR0 Fld(2, 14) /* SDRAM write recovery 0/1 */
1416 #define MDCNFG_SA1110_DE2 0x00010000 /* DRAM Enable bank 0 */
1417 #define MDCNFG_SA1110_DE3 0x00020000 /* DRAM Enable bank 1 */
1418 #define MDCNFG_SA1110_DTIM2 0x00040000 /* DRAM timing type 0/1 */
1419 #define MDCNFG_SA1110_DWID2 0x00080000 /* DRAM bus width 0/1 */
1421 /* bank 0/1 */
1422 #define MDCNFG_SA1110_CDB22 0x00800000 /* Mem Clock divide by 2 0/1 */
1423 #define MDCNFG_SA1110_TRP2 Fld(3, 24) /* RAS precharge 0/1 */
1425 /* deassertion 0/1 */
1426 #define MDCNFG_SA1110_TWR2 Fld(2, 30) /* SDRAM write recovery 0/1 */
1433 * MSC0 Memory system: Static memory Control register 0
1443 #define MSC0 __REG(0xa0000010) /* Static memory Control reg. 0 */
1444 #define MSC1 __REG(0xa0000014) /* Static memory Control reg. 1 */
1445 #define MSC2 __REG(0xa000002c) /* Static memory Control reg. 2, not contiguous */
1447 #define MSC_Bnk(Nb) /* static memory Bank [0..3] */ \
1449 #define MSC0_Bnk0 MSC_Bnk (0) /* static memory Bank 0 */
1454 #define MSC_RT Fld (2, 0) /* ROM/static memory Type */
1456 (0 << FShft (MSC_RT))
1463 #define MSC_RBW 0x0004 /* ROM/static memory Bus Width */
1464 #define MSC_32BitStMem (MSC_RBW*0) /* 32-Bit Static Memory */
1492 #define MSC_Rec(Tcpu) /* Recovery time [0..28 Tcpu] */ \
1494 #define MSC_CeilRec(Tcpu) /* Ceil. of Rec [0..28 Tcpu] */ \
1513 #define MECR __REG(0xA0000018) /* Expansion memory bus (PCMCIA) Configuration Reg. */
1515 #define MECR_PCMCIA(Nb) /* PCMCIA [0..1] */ \
1517 #define MECR_PCMCIA0 MECR_PCMCIA (0) /* PCMCIA 0 */
1520 #define MECR_BSIO Fld (5, 0) /* BCLK Select I/O - 1 [Tmem] */
1541 #define MDREFR __REG(0xA000001C)
1543 #define MDREFR_TRASR Fld (4, 0)
1561 #define DMA_SIZE (6 * 0x20)
1562 #define DMA_PHYS 0xb0000000
1569 * LCCR0 Liquid Crystal Display (LCD) Control Register 0
1628 #define LCD_PGrey Fld (4, 0) /* LCD Palette entry Grey value */
1629 #define LCD_PBlue Fld (4, 0) /* LCD Palette entry Blue value */
1634 (0 << FShft (LCD_PBS))
1640 #define LCD_Int0_0 0x0 /* LCD Intensity = 0.0% = 0 */
1641 #define LCD_Int11_1 0x1 /* LCD Intensity = 11.1% = 1/9 */
1642 #define LCD_Int20_0 0x2 /* LCD Intensity = 20.0% = 1/5 */
1643 #define LCD_Int26_7 0x3 /* LCD Intensity = 26.7% = 4/15 */
1644 #define LCD_Int33_3 0x4 /* LCD Intensity = 33.3% = 3/9 */
1645 #define LCD_Int40_0 0x5 /* LCD Intensity = 40.0% = 2/5 */
1646 #define LCD_Int44_4 0x6 /* LCD Intensity = 44.4% = 4/9 */
1647 #define LCD_Int50_0 0x7 /* LCD Intensity = 50.0% = 1/2 */
1648 #define LCD_Int55_6 0x8 /* LCD Intensity = 55.6% = 5/9 */
1649 #define LCD_Int60_0 0x9 /* LCD Intensity = 60.0% = 3/5 */
1650 #define LCD_Int66_7 0xA /* LCD Intensity = 66.7% = 6/9 */
1651 #define LCD_Int73_3 0xB /* LCD Intensity = 73.3% = 11/15 */
1652 #define LCD_Int80_0 0xC /* LCD Intensity = 80.0% = 4/5 */
1653 #define LCD_Int88_9 0xD /* LCD Intensity = 88.9% = 8/9 */
1654 #define LCD_Int100_0 0xE /* LCD Intensity = 100.0% = 1 */
1655 #define LCD_Int100_0A 0xF /* LCD Intensity = 100.0% = 1 */
1658 #define LCCR0_LEN 0x00000001 /* LCD ENable */
1659 #define LCCR0_CMS 0x00000002 /* Color/Monochrome display Select */
1660 #define LCCR0_Color (LCCR0_CMS*0) /* Color display */
1662 #define LCCR0_SDS 0x00000004 /* Single/Dual panel display */
1664 #define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */
1666 #define LCCR0_LDM 0x00000008 /* LCD Disable done (LDD) */
1668 #define LCCR0_BAM 0x00000010 /* Base Address update (BAU) */
1670 #define LCCR0_ERM 0x00000020 /* LCD ERror (BER, IOL, IUL, IOU, */
1673 #define LCCR0_PAS 0x00000080 /* Passive/Active display Select */
1674 #define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */
1676 #define LCCR0_BLE 0x00000100 /* Big/Little Endian select */
1677 #define LCCR0_LtlEnd (LCCR0_BLE*0) /* Little Endian frame buffer */
1679 #define LCCR0_DPD 0x00000200 /* Double Pixel Data (monochrome */
1681 #define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */
1688 /* [0..510 Tcpu] */ \
1691 #define LCSR_LDD 0x00000001 /* LCD Disable Done */
1692 #define LCSR_BAU 0x00000002 /* Base Address Update (read) */
1693 #define LCSR_BER 0x00000004 /* Bus ERror */
1694 #define LCSR_ABC 0x00000008 /* AC Bias clock Count */
1695 #define LCSR_IOL 0x00000010 /* Input FIFO Over-run Lower */
1697 #define LCSR_IUL 0x00000020 /* Input FIFO Under-run Lower */
1699 #define LCSR_IOU 0x00000040 /* Input FIFO Over-run Upper */
1701 #define LCSR_IUU 0x00000080 /* Input FIFO Under-run Upper */
1703 #define LCSR_OOL 0x00000100 /* Output FIFO Over-run Lower */
1705 #define LCSR_OUL 0x00000200 /* Output FIFO Under-run Lower */
1707 #define LCSR_OOU 0x00000400 /* Output FIFO Over-run Upper */
1709 #define LCSR_OUU 0x00000800 /* Output FIFO Under-run Upper */
1731 #define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
1742 /* [0..255 Tln] */ \
1747 /* [0..255 Tln] */ \
1750 #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor/2 - 2 */
1776 (0 << FShft (LCCR3_API))
1780 #define LCCR3_VSP 0x00100000 /* Vertical Synchronization pulse */
1782 #define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */
1786 #define LCCR3_HSP 0x00200000 /* Horizontal Synchronization */
1788 #define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */
1792 #define LCCR3_PCP 0x00400000 /* Pixel Clock Polarity (L_PCLK) */
1793 #define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */
1795 #define LCCR3_OEP 0x00800000 /* Output Enable Polarity (L_BIAS, */
1797 #define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */