Lines Matching full:sdram
15 #define MDCNFG (SMEMC_VIRT + 0x00) /* SDRAM Configuration Register 0 */
16 #define MDREFR (SMEMC_VIRT + 0x04) /* SDRAM Refresh Control Register */
21 #define SXLCR (SMEMC_VIRT + 0x18) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
30 #define MDMRS (SMEMC_VIRT + 0x40) /* MRS value to be written to SDRAM */
52 #define MDCNFG_DE0 (1 << 0) /* SDRAM Bank 0 Enable */
53 #define MDCNFG_DE1 (1 << 1) /* SDRAM Bank 1 Enable */
54 #define MDCNFG_DE2 (1 << 16) /* SDRAM Bank 2 Enable */
55 #define MDCNFG_DE3 (1 << 17) /* SDRAM Bank 3 Enable */
58 #define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
59 #define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
60 #define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
61 #define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */
62 #define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */