Lines Matching +full:run +full:- +full:control

1 /* SPDX-License-Identifier: GPL-2.0-only */
16 #define MDREFR		(SMEMC_VIRT + 0x04)  /* SDRAM Refresh Control Register */
17 #define MSC0		(SMEMC_VIRT + 0x08)  /* Static Memory Control Register 0 */
18 #define MSC1		(SMEMC_VIRT + 0x0C)  /* Static Memory Control Register 1 */
19 #define MSC2		(SMEMC_VIRT + 0x10)  /* Static Memory Control Register 2 */
21 #define SXLCR		(SMEMC_VIRT + 0x18)  /* LCR value to be written to SDRAM-Timing Synchronous Flash */
22 #define SXCNFG		(SMEMC_VIRT + 0x1C)  /* Synchronous Static Memory Control Register */
31 #define BOOT_DEF	(SMEMC_VIRT + 0x44)  /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SE…
49 #define MECR_NOS	(1 << 0)	/* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
50 #define MECR_CIT	(1 << 1)	/* Card Is There: 0 -> no card, 1 -> card inserted */
57 #define MDREFR_K0DB4	(1 << 29)	/* SDCLK0 Divide by 4 Control/Status */
58 #define MDREFR_K2FREE	(1 << 25)	/* SDRAM Free-Running Control */
59 #define MDREFR_K1FREE	(1 << 24)	/* SDRAM Free-Running Control */
60 #define MDREFR_K0FREE	(1 << 23)	/* SDRAM Free-Running Control */
61 #define MDREFR_SLFRSH	(1 << 22)	/* SDRAM Self-Refresh Control/Status */
62 #define MDREFR_APD	(1 << 20)	/* SDRAM/SSRAM Auto-Power-Down Enable */
63 #define MDREFR_K2DB2	(1 << 19)	/* SDCLK2 Divide by 2 Control/Status */
64 #define MDREFR_K2RUN	(1 << 18)	/* SDCLK2 Run Control/Status */
65 #define MDREFR_K1DB2	(1 << 17)	/* SDCLK1 Divide by 2 Control/Status */
66 #define MDREFR_K1RUN	(1 << 16)	/* SDCLK1 Run Control/Status */
67 #define MDREFR_E1PIN	(1 << 15)	/* SDCKE1 Level Control/Status */
68 #define MDREFR_K0DB2	(1 << 14)	/* SDCLK0 Divide by 2 Control/Status */
69 #define MDREFR_K0RUN	(1 << 13)	/* SDCLK0 Run Control/Status */
70 #define MDREFR_E0PIN	(1 << 12)	/* SDCKE0 Level Control/Status */