1 // SPDX-License-Identifier: GPL-2.0-only
5  * Copyright (C) 2010-2011 Texas Instruments, Inc.
18 #include "prm-regbits-24xx.h"
22  * omap2_prm_is_hardreset_asserted - read the HW reset line state of
24  * @shift: register bit shift corresponding to the reset line to check
31  * -EINVAL if called while running on a non-OMAP2/3 chip.
40  * omap2_prm_assert_hardreset - assert the HW reset line of a submodule
41  * @shift: register bit shift corresponding to the reset line to assert
47  * reset line to be asserted / deasserted in order to fully enable the
48  * IP.  These modules may have multiple hard-reset lines that reset
50  * place the submodule into reset.  Returns 0 upon success or -EINVAL
55 	u32 mask;  in omap2_prm_assert_hardreset()  local
57 	mask = 1 << shift;  in omap2_prm_assert_hardreset()
58 	omap2_prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL);  in omap2_prm_assert_hardreset()
64  * omap2_prm_deassert_hardreset - deassert a submodule hardreset line and wait
66  * @rst_shift: register bit shift corresponding to the reset line to deassert
70  * @rst_offset: reset register offset, not used for OMAP2
71  * @st_offset: reset status register offset, not used for OMAP2
74  * reset line to be asserted / deasserted in order to fully enable the
75  * IP.  These modules may have multiple hard-reset lines that reset
77  * take the submodule out of reset and wait until the PRCM indicates
78  * that the reset has completed before returning.  Returns 0 upon success or
79  * -EINVAL upon an argument error, -EEXIST if the submodule was already out
80  * of reset, or -EBUSY if the submodule did not exit reset promptly.
91 	/* Check the current status to avoid de-asserting the line twice */  in omap2_prm_deassert_hardreset()
93 		return -EEXIST;  in omap2_prm_deassert_hardreset()
95 	/* Clear the reset status by writing 1 to the status bit */  in omap2_prm_deassert_hardreset()
97 	/* de-assert the reset control line */  in omap2_prm_deassert_hardreset()
104 	return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;  in omap2_prm_deassert_hardreset()
108 /* Powerdomain low-level functions */
118 	omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,  in omap2_pwrdm_set_mem_onst()
131 	omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,  in omap2_pwrdm_set_mem_retst()
143 	return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST,  in omap2_pwrdm_read_mem_pwrst()
153 	return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,  in omap2_pwrdm_read_mem_retst()
162 	omap2_prm_rmw_mod_reg_bits(OMAP_LOGICRETSTATE_MASK, v, pwrdm->prcm_offs,  in omap2_pwrdm_set_logic_retst()
174 	 * via a callback and a periodic timer check -- how long do we expect  in omap2_pwrdm_wait_transition()
179 	while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs, OMAP2_PM_PWSTST) &  in omap2_pwrdm_wait_transition()
186 		       pwrdm->name);  in omap2_pwrdm_wait_transition()
187 		return -EAGAIN;  in omap2_pwrdm_wait_transition()
198 	omap2_prm_set_mod_reg_bits((1 << clkdm2->dep_bit),  in omap2_clkdm_add_wkdep()
199 				   clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);  in omap2_clkdm_add_wkdep()
206 	omap2_prm_clear_mod_reg_bits((1 << clkdm2->dep_bit),  in omap2_clkdm_del_wkdep()
207 				     clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);  in omap2_clkdm_del_wkdep()
214 	return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,  in omap2_clkdm_read_wkdep()
215 					     PM_WKDEP, (1 << clkdm2->dep_bit));  in omap2_clkdm_read_wkdep()
222 	u32 mask = 0;  in omap2_clkdm_clear_all_wkdeps()  local
224 	for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {  in omap2_clkdm_clear_all_wkdeps()
225 		if (!cd->clkdm)  in omap2_clkdm_clear_all_wkdeps()
229 		mask |= 1 << cd->clkdm->dep_bit;  in omap2_clkdm_clear_all_wkdeps()
230 		cd->wkdep_usecount = 0;  in omap2_clkdm_clear_all_wkdeps()
233 	omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,  in omap2_clkdm_clear_all_wkdeps()