Lines Matching +full:wugen +full:- +full:mpu
1 // SPDX-License-Identifier: GPL-2.0-only
19 #include <linux/irqchip/arm-gic.h>
24 #include <asm/hardware/cache-l2x0.h>
29 #include "omap-wakeupgen.h"
35 #include "omap4-sar-layout.h"
36 #include "omap-secure.h"
60 * data writes from the MPU. These asynchronous bridges can be found on
61 * paths between the MPU to EMIF, and the MPU to L3 interconnects.
63 * We need to be careful about re-ordering which can happen as a result
74 * The mb() and wmb() barriers only operate only on the MPU->MA->EMIF
87 * OMAP4 Errata i688 - asynchronous bridge corruption when entering WFI.
95 * Async bridges can be found on paths between MPU to EMIF and MPU to L3
102 * The work-around for this errata needs all the initiators connected
107 * In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained.
112 * operates on both the MPU->MA->EMIF path but also the MPU->OCP path
132 np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu"); in omap4_sram_init()
257 return -ENOMEM; in omap_l2_cache_init()
278 * multi-omap builds in omap4_sar_ram_init()
294 { .compatible = "ti,omap4-wugen-mpu", },
295 { .compatible = "ti,omap5-wugen-mpu", },
307 pr_err("No WUGEN found in DT, system will misbehave.\n"); in omap_gic_of_init()
315 np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic"); in omap_gic_of_init()
320 np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-twd-timer"); in omap_gic_of_init()