Lines Matching +full:can +full:- +full:secondary

1 // SPDX-License-Identifier: GPL-2.0-only
19 #include <linux/irqchip/arm-gic.h>
25 #include "omap-secure.h"
26 #include "omap-wakeupgen.h"
87 	 * BIT(27) - Disables streaming. All write-allocate lines allocate in  in omap5_erratum_workaround_801819()
89 	 * BIT(25) - Disables streaming. All write-allocate lines allocate in  in omap5_erratum_workaround_801819()
110  * ICIALLU) to activate the workaround for secondary Core.
115  * In General Purpose(GP) devices, ACR bit settings can only be done
150 	 * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA  in omap4_secondary_init()
153 	 * OMAP443X GP devices- SMP bit isn't accessible.  in omap4_secondary_init()
154 	 * OMAP446X GP devices - SMP bit access is enabled on both CPUs.  in omap4_secondary_init()
162 		 * Configure the CNTFRQ register for the secondary cpu's which  in omap4_secondary_init()
180 	 * Update the AuxCoreBoot0 with boot state for secondary core.  in omap4_boot_secondary()
181 	 * omap4_secondary_startup() routine will hold the secondary core till  in omap4_boot_secondary()
201 	 * wake-up. To wakeup CPU1, CPU0 forces the CPU1 clockdomain to  in omap4_boot_secondary()
204 	 * More details can be found in OMAP4430 TRM - Version J  in omap4_boot_secondary()
214 		 * bit 1 == Non-Secure Enable  in omap4_boot_secondary()
215 		 * The Non-Secure banked register has not changed  in omap4_boot_secondary()
217 		 * GIC restoration will cause a problem to CPU0 Non-Secure SW.  in omap4_boot_secondary()
221 		 * 2) CPU1 must re-enable the GIC distributor on  in omap4_boot_secondary()
256  * Initialise the CPU possible map early - this describes the CPUs
267 		 * Currently we can't call ioremap here because  in omap4_smp_init_cpus()
289  * For now, just make sure the start-up address is not within the booting
302  * We may need to reset CPU1 before configuring, otherwise kexec boot can end
303  * up trying to use old kernel startup address or suspend-resume will
344 	if (!needs_reset || !c->cpu1_rstctrl_va)  in omap4_smp_maybe_reset_cpu1()
350 	writel_relaxed(1, c->cpu1_rstctrl_va);  in omap4_smp_maybe_reset_cpu1()
351 	readl_relaxed(c->cpu1_rstctrl_va);  in omap4_smp_maybe_reset_cpu1()
352 	writel_relaxed(0, c->cpu1_rstctrl_va);  in omap4_smp_maybe_reset_cpu1()
372 	cfg.cpu1_rstctrl_pa = c->cpu1_rstctrl_pa;  in omap4_smp_prepare_cpus()
373 	cfg.startup_addr = c->startup_addr;  in omap4_smp_prepare_cpus()
387 	 * Initialise the SCU and wake up the secondary core using  in omap4_smp_prepare_cpus()
396 	 * Write the address of secondary startup routine into the  in omap4_smp_prepare_cpus()
398 	 * on secondary core once out of WFE  in omap4_smp_prepare_cpus()