Lines Matching +full:wait +full:- +full:on +full:- +full:read
1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2009-2014 Texas Instruments, Inc.
10 * Interface functions needed for the SMP. This file is based on arm
21 /* Physical address needed since MMU not enabled yet on secondary core */
43 wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0 label
49 bne wait
58 .arch armv7-a
61 wait_2: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
84 smc #0 @ read from AuxCoreBoot0
92 * we've been released from the wait loop,secondary_stack
101 smc #0 @ read from AuxCoreBoot0
113 * bit 1 == Non-Secure Enable
114 * The Non-Secure banked register has not changed
115 * Because the ROM Code is based on the r1pX GIC, the CPU1
116 * GIC restoration will cause a problem to CPU0 Non-Secure SW.
120 * 2) CPU1 must re-enable the GIC distributor on
129 * we've been released from the wait loop,secondary_stack