Lines Matching +full:0 +full:xff000000
72 mov r4, #TCMIF_ASM_BASE & 0xff000000
73 orr r4, r4, #TCMIF_ASM_BASE & 0x00ff0000
74 orr r4, r4, #TCMIF_ASM_BASE & 0x0000ff00
78 ldr r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
79 bic r5, r5, #PDE_BIT & 0xff
80 str r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
83 and r5, r5, #PWD_EN_BIT & 0xff
84 str r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
87 ldr r5, [r4, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
88 orr r5, r5, #SELF_REFRESH_MODE & 0xff000000
89 orr r5, r5, #SELF_REFRESH_MODE & 0x000000ff
90 str r5, [r4, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
93 ldr r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
94 orr r5, r5, #IDLE_EMIFS_REQUEST & 0xff
95 str r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
98 mov r4, #CLKGEN_REG_ASM_BASE & 0xff000000
99 orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
100 orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
103 mov r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff
104 orr r5, r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff00
105 strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
108 mov r3, #OMAP1510_DEEP_SLEEP_REQUEST & 0xff
109 orr r3, r3, #OMAP1510_DEEP_SLEEP_REQUEST & 0xff00
110 strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
112 mov r5, #IDLE_WAIT_CYCLES & 0xff
113 orr r5, r5, #IDLE_WAIT_CYCLES & 0xff00
121 mov r2, #0
122 mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt
129 strh r1, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
130 strh r0, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
147 mov r4, #0
148 mcr p15, 0, r0, c7, c10, 4
152 mov r6, #TCMIF_ASM_BASE & 0xff000000
153 orr r6, r6, #TCMIF_ASM_BASE & 0x00ff0000
154 orr r6, r6, #TCMIF_ASM_BASE & 0x0000ff00
157 ldr r7, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
158 orr r9, r7, #SELF_REFRESH_MODE & 0xff000000
159 orr r9, r9, #SELF_REFRESH_MODE & 0x000000ff
160 str r9, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
163 ldr r8, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
164 orr r9, r8, #IDLE_EMIFS_REQUEST & 0xff
165 str r9, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
168 mov r4, #CLKGEN_REG_ASM_BASE & 0xff000000
169 orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
170 orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
173 @ Do not disable PERCK (0x04)
174 mov r5, #OMAP1610_IDLECT2_SLEEP_VAL & 0xff
175 orr r5, r5, #OMAP1610_IDLECT2_SLEEP_VAL & 0xff00
176 strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
179 mov r3, #OMAP1610_IDLECT1_SLEEP_VAL & 0xff
180 orr r3, r3, #OMAP1610_IDLECT1_SLEEP_VAL & 0xff00
181 strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
187 mov r2, #0
188 mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt
278 strh r1, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
279 strh r0, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
282 str r7, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
283 str r8, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]