Lines Matching +full:sram +full:- +full:proc
1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-omap1/clock_data.c
5 * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
10 * - Clocks that are only available on some chips should be marked with the
18 #include <linux/clk-provider.h>
21 #include <linux/soc/ti/omap1-io.h>
23 #include <asm/mach-types.h> /* for machine_is_* */
30 #include "sram.h"
32 /* Some ARM_IDLECT1 bit shifts - used in struct arm_idlect1_clk */
43 /* Some MOD_CONF_CTRL_0 bit shifts - used in struct clk.enable_bit */
50 /* Some MOD_CONF_CTRL_1 bit shifts - used in struct clk.enable_bit */
53 /* Some OTG_SYSCON_2-specific bit fields */
56 /* Some SOFT_REQ_REG bit fields - used in struct clk.enable_bit */
69 #define SOFT_COM_REQ_SHIFT 1 /* sys_ck gate for com proc? */
91 * FIXME: This clock seems to be necessary but no-one has asked for its
141 * FIXME: This clock seems to be necessary but no-one has asked for its
262 /* No-idle controlled by "tc_ck" */
267 /* No-idle controlled by "tc_ck" */
282 * FIXME: This clock seems to be necessary but no-one has asked for its
283 * activation. [ pm.c (SRAM), CCP, Camera ]
294 /* No-idle controlled by "tc_ck" */
360 * XXX The enable_bit here is misused - it simply switches between 12MHz
377 * XXX The enable_bit here is misused - it simply switches between 12MHz
396 * XXX The enable_bit here is misused - it simply switches between 12MHz
413 * XXX The enable_bit here is misused - it simply switches between 12MHz
430 * XXX The enable_bit here is misused - it simply switches between 12MHz
473 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
602 /* non-ULPD clocks */
654 CLK("mmci-omap.0", "fck", &mmc1_ck.hw, CK_16XX | CK_1510 | CK_310),
655 CLK("mmci-omap.0", "fck", &mmc3_ck.hw, CK_7XX),
656 CLK("mmci-omap.0", "ick", &armper_ck.clk.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
657 CLK("mmci-omap.1", "fck", &mmc2_ck.hw, CK_16XX),
658 CLK("mmci-omap.1", "ick", &armper_ck.clk.hw, CK_16XX),
669 CLK("omap-mcbsp.1", "ick", &dspper_ck.hw, CK_16XX),
670 CLK("omap-mcbsp.1", "ick", &dummy_ck.hw, CK_1510 | CK_310),
671 CLK("omap-mcbsp.2", "ick", &armper_ck.clk.hw, CK_16XX),
672 CLK("omap-mcbsp.2", "ick", &dummy_ck.hw, CK_1510 | CK_310),
673 CLK("omap-mcbsp.3", "ick", &dspper_ck.hw, CK_16XX),
674 CLK("omap-mcbsp.3", "ick", &dummy_ck.hw, CK_1510 | CK_310),
675 CLK("omap-mcbsp.1", "fck", &dspxor_ck.hw, CK_16XX | CK_1510 | CK_310),
676 CLK("omap-mcbsp.2", "fck", &armper_ck.clk.hw, CK_16XX | CK_1510 | CK_310),
677 CLK("omap-mcbsp.3", "fck", &dspxor_ck.hw, CK_16XX | CK_1510 | CK_310),
743 * after the SRAM is initialized. in omap1_clk_init()
785 * of the ARM_IDLECT2 register must be set to zero. The power-on in omap1_clk_init()
791 if (!(c->cpu & cpu_mask)) in omap1_clk_init()
794 if (c->lk.clk_hw->init) { /* NULL if provider already registered */ in omap1_clk_init()
795 const struct clk_init_data *init = c->lk.clk_hw->init; in omap1_clk_init()
796 const char *name = c->lk.clk_hw->init->name; in omap1_clk_init()
799 err = clk_hw_register(NULL, c->lk.clk_hw); in omap1_clk_init()
803 c->lk.clk_hw->init = init; in omap1_clk_init()
808 clk_hw_register_clkdev(c->lk.clk_hw, c->lk.con_id, c->lk.dev_id); in omap1_clk_init()
826 * Reprogramming the DPLL is tricky, it must be done from SRAM. in omap1_clk_late_init()