Lines Matching +full:0 +full:xf0010000
26 #define SDRAM_CONFIG_OFFS 0x0
28 #define SDRAM_OPERATION_OFFS 0x18
29 #define SDRAM_OPERATION_SELF_REFRESH 0x7
30 #define SDRAM_DLB_EVICTION_OFFS 0x30c
31 #define SDRAM_DLB_EVICTION_THRESHOLD_MASK 0xff
64 srcmd &= ~0x1F; in mvebu_pm_powerdown()
69 return 0; in mvebu_pm_powerdown()
72 #define BOOT_INFO_ADDR 0x3000
73 #define BOOT_MAGIC_WORD 0xdeadb002
74 #define BOOT_MAGIC_LIST_END 0xffffffff
78 * base, which is why we hardcode the 0xd0000000 base address, the one
81 #define MBUS_WINDOW_12_CTRL 0xd00200b0
82 #define MBUS_INTERNAL_REG_ADDRESS 0xd0020080
84 #define SDRAM_WIN_BASE_REG(x) (0x20180 + (0x8*x))
85 #define SDRAM_WIN_CTRL_REG(x) (0x20184 + (0x8*x))
97 * platform. In the mvebu-mbus DT binding, 0xf0010000 in mvebu_internal_reg_base()
100 in_addr[0] = cpu_to_be32(0xf0010000); in mvebu_internal_reg_base()
101 in_addr[1] = 0x0; in mvebu_internal_reg_base()
126 * to 0xf1000000. However, out of reset, window 12 starts at in mvebu_pm_store_armadaxp_bootinfo()
127 * 0xf0000000 and ends at 0xf7ffffff, which would overlap with in mvebu_pm_store_armadaxp_bootinfo()
131 writel(0x0, store_addr++); in mvebu_pm_store_armadaxp_bootinfo()
161 return 0; in mvebu_pm_store_bootinfo()
174 cpu_suspend(0, mvebu_pm_powerdown); in mvebu_enter_suspend()
183 return 0; in mvebu_enter_suspend()
198 return 0; in mvebu_pm_enter()
209 return 0; in mvebu_pm_valid()
227 return 0; in mvebu_pm_init()
244 if (of_address_to_resource(np, 0, &res)) { in mvebu_pm_suspend_init()
266 return 0; in mvebu_pm_suspend_init()