Lines Matching refs:r11
78 ldr r11, [r0, #PM_INFO_MX6Q_L2_V_OFFSET]
79 teq r11, #0
82 str r6, [r11, #L2X0_CACHE_SYNC]
84 ldr r6, [r11, #L2X0_CACHE_SYNC]
96 ldreq r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
97 ldrne r11, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET]
105 str r9, [r11, r8]
110 ldreq r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
111 ldrne r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET]
118 ldr r6, [r11, r7]
120 str r6, [r11, r7]
122 ldr r6, [r11, r7]
127 ldr r6, [r11, r7]
129 str r6, [r11, r7]
131 ldr r6, [r11, r7]
136 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
138 str r7, [r11, #MX6Q_MMDC_MAPSR]
140 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
145 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
147 str r7, [r11, #MX6Q_MMDC_MAPSR]
172 ldr r11, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET]
173 ldr r6, [r11, #0x0]
174 ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
175 ldr r6, [r11, #0x0]
176 ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
177 ldr r6, [r11, #0x0]
180 ldr r11, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET]
182 str r9, [r11, #MX6Q_SRC_GPR1]
183 str r1, [r11, #MX6Q_SRC_GPR2]
188 ldr r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
193 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
195 str r7, [r11, #MX6Q_MMDC_MAPSR]
198 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
200 str r7, [r11, #MX6Q_MMDC_MAPSR]
203 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
207 ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
217 str r6, [r11, r9]
225 str r6, [r11, r9]
227 str r6, [r11, r9]
230 str r6, [r11, r9]
240 ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
241 ldr r6, [r11, #MX6Q_GPC_IMR1]
242 ldr r7, [r11, #MX6Q_GPC_IMR2]
243 ldr r8, [r11, #MX6Q_GPC_IMR3]
244 ldr r9, [r11, #MX6Q_GPC_IMR4]
247 str r10, [r11, #MX6Q_GPC_IMR1]
248 str r10, [r11, #MX6Q_GPC_IMR2]
249 str r10, [r11, #MX6Q_GPC_IMR3]
250 str r10, [r11, #MX6Q_GPC_IMR4]
258 ldr r11, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET]
259 ldr r10, [r11, #MX6Q_CCM_CCR]
262 str r10, [r11, #MX6Q_CCM_CCR]
265 ldr r10, [r11, #MX6Q_CCM_CCR]
267 str r10, [r11, #MX6Q_CCM_CCR]
270 ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
271 str r6, [r11, #MX6Q_GPC_IMR1]
272 str r7, [r11, #MX6Q_GPC_IMR2]
273 str r8, [r11, #MX6Q_GPC_IMR3]
274 str r9, [r11, #MX6Q_GPC_IMR4]
322 ldr r11, [r0, #PM_INFO_MX6Q_SRC_P_OFFSET]
324 str r7, [r11, #MX6Q_SRC_GPR1]
325 str r7, [r11, #MX6Q_SRC_GPR2]