Lines Matching +full:0 +full:x584
26 #define MXC_CCM_CLPCR 0x54
27 #define MXC_CCM_CLPCR_LPM_OFFSET 0
28 #define MXC_CCM_CLPCR_LPM_MASK 0x3
30 #define MXC_CCM_CLPCR_VSTBY (0x1 << 8)
31 #define MXC_CCM_CLPCR_SBYOS (0x1 << 6)
33 #define MXC_CORTEXA8_PLAT_LPC 0xc
34 #define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0)
37 #define MXC_SRPG_NEON_SRPGCR 0x280
38 #define MXC_SRPG_ARM_SRPGCR 0x2a0
39 #define MXC_SRPG_EMPGC0_SRPGCR 0x2c0
40 #define MXC_SRPG_EMPGC1_SRPGCR 0x2d0
74 #define MX53_DSE_HIGHZ_MASK (0x7 << 19)
75 {.offset = 0x584, .clear = MX53_DSE_HIGHZ_MASK}, /* DQM0 */
76 {.offset = 0x594, .clear = MX53_DSE_HIGHZ_MASK}, /* DQM1 */
77 {.offset = 0x560, .clear = MX53_DSE_HIGHZ_MASK}, /* DQM2 */
78 {.offset = 0x554, .clear = MX53_DSE_HIGHZ_MASK}, /* DQM3 */
79 {.offset = 0x574, .clear = MX53_DSE_HIGHZ_MASK}, /* CAS */
80 {.offset = 0x588, .clear = MX53_DSE_HIGHZ_MASK}, /* RAS */
81 {.offset = 0x578, .clear = MX53_DSE_HIGHZ_MASK}, /* SDCLK_0 */
82 {.offset = 0x570, .clear = MX53_DSE_HIGHZ_MASK}, /* SDCLK_1 */
84 {.offset = 0x580, .clear = MX53_DSE_HIGHZ_MASK}, /* SDODT0 */
85 {.offset = 0x564, .clear = MX53_DSE_HIGHZ_MASK}, /* SDODT1 */
86 {.offset = 0x57c, .clear = MX53_DSE_HIGHZ_MASK}, /* SDQS0 */
87 {.offset = 0x590, .clear = MX53_DSE_HIGHZ_MASK}, /* SDQS1 */
88 {.offset = 0x568, .clear = MX53_DSE_HIGHZ_MASK}, /* SDQS2 */
89 {.offset = 0x558, .clear = MX53_DSE_HIGHZ_MASK}, /* SDSQ3 */
90 {.offset = 0x6f0, .clear = MX53_DSE_HIGHZ_MASK}, /* GRP_ADDS */
91 {.offset = 0x718, .clear = MX53_DSE_HIGHZ_MASK}, /* GRP_BODS */
92 {.offset = 0x71c, .clear = MX53_DSE_HIGHZ_MASK}, /* GRP_B1DS */
93 {.offset = 0x728, .clear = MX53_DSE_HIGHZ_MASK}, /* GRP_B2DS */
94 {.offset = 0x72c, .clear = MX53_DSE_HIGHZ_MASK}, /* GRP_B3DS */
97 {.offset = 0x720, .clear = MX53_DSE_HIGHZ_MASK, .set = 1 << 19}, /* CTLDS */
101 .ccm_addr = 0x73fd4000,
102 .cortex_addr = 0x83fa0000,
103 .gpc_addr = 0x73fd8000,
107 .ccm_addr = 0x53fd4000,
108 .cortex_addr = 0x63fa0000,
109 .gpc_addr = 0x53fd8000,
110 .m4if_addr = 0x63fd8000,
111 .iomuxc_addr = 0x53fa8000,
148 int stop_mode = 0; in mx5_cpu_lp_set()
166 ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET; in mx5_cpu_lp_set()
173 ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET; in mx5_cpu_lp_set()
176 stop_mode = 0; in mx5_cpu_lp_set()
178 ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET; in mx5_cpu_lp_set()
179 ccm_clpcr |= 0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET; in mx5_cpu_lp_set()
187 ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET; in mx5_cpu_lp_set()
226 imx_writel(0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR); in mx5_suspend_enter()
227 imx_writel(0, gpc_base + MXC_SRPG_EMPGC1_SRPGCR); in mx5_suspend_enter()
240 return 0; in mx5_suspend_enter()
279 int ret = 0; in imx_suspend_alloc_ocram()
332 return 0; in imx5_suspend_init()
366 return 0; in imx5_suspend_init()
408 return 0; in imx5_pm_common_init()