Lines Matching +full:0 +full:x79000000
13 * 0xff800000 0x40000000 1MB X-Bus
14 * 0xff000000 0x7c000000 1MB PCI I/O space
15 * 0xfe000000 0x42000000 1MB CSR
16 * 0xfd000000 0x78000000 1MB Outbound write flush (not supported)
17 * 0xfc000000 0x79000000 1MB PCI IACK/special space
18 * 0xfb000000 0x7a000000 16MB PCI Config type 1
19 * 0xfa000000 0x7b000000 16MB PCI Config type 0
20 * 0xf9000000 0x50000000 1MB Cache flush
21 * 0xf0000000 0x80000000 16MB ISA memory
24 #define XBUS_SIZE 0x00100000
25 #define XBUS_BASE 0xff800000
27 #define ARMCSR_SIZE 0x00100000
28 #define ARMCSR_BASE 0xfe000000
30 #define WFLUSH_SIZE 0x00100000
31 #define WFLUSH_BASE 0xfd000000
33 #define PCIIACK_SIZE 0x00100000
34 #define PCIIACK_BASE 0xfc000000
36 #define PCICFG1_SIZE 0x01000000
37 #define PCICFG1_BASE 0xfb000000
39 #define PCICFG0_SIZE 0x01000000
40 #define PCICFG0_BASE 0xfa000000
42 #define PCIMEM_SIZE 0x01000000
43 #define PCIMEM_BASE 0xf0000000
45 #define XBUS_CS2 0x40012000
47 #define XBUS_SWITCH ((volatile unsigned char *)(XBUS_BASE + 0x12000))
53 #define UNCACHEABLE_ADDR (ARMCSR_BASE + 0x108) /* CSR_ROMBASEMASK */
57 #define PIC_LO 0x20
58 #define PIC_MASK_LO 0x21
59 #define PIC_HI 0xA0
60 #define PIC_MASK_HI 0xA1
63 #define GPIO_CCLK 0x800
64 #define GPIO_DSCLK 0x400
65 #define GPIO_E2CLK 0x200
66 #define GPIO_IOLOAD 0x100
67 #define GPIO_RED_LED 0x080
68 #define GPIO_WDTIMER 0x040
69 #define GPIO_DATA 0x020
70 #define GPIO_IOCLK 0x010
71 #define GPIO_DONE 0x008
72 #define GPIO_FAN 0x004
73 #define GPIO_GREEN_LED 0x002
74 #define GPIO_RESET 0x001