1 // SPDX-License-Identifier: GPL-2.0-only
3  * arch/arm/mach-dove/pcie.c
17 #include <plat/addr-map.h>
18 #include "irqs.h"
19 #include "bridge-regs.h"
35 static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)  in dove_pcie_setup()  argument
40 	if (nr >= num_pcie_ports)  in dove_pcie_setup()
43 	pp = &pcie_port[nr];  in dove_pcie_setup()
44 	sys->private_data = pp;  in dove_pcie_setup()
45 	pp->root_bus_nr = sys->busnr;  in dove_pcie_setup()
50 	orion_pcie_set_local_bus_nr(pp->base, sys->busnr);  in dove_pcie_setup()
52 	orion_pcie_setup(pp->base);  in dove_pcie_setup()
54 	realio.start = sys->busnr * SZ_64K;  in dove_pcie_setup()
55 	realio.end = realio.start + SZ_64K - 1;  in dove_pcie_setup()
56 	pci_remap_iospace(&realio, pp->index == 0 ? DOVE_PCIE0_IO_PHYS_BASE :  in dove_pcie_setup()
62 	snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),  in dove_pcie_setup()
63 		 "PCIe %d MEM", pp->index);  in dove_pcie_setup()
64 	pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;  in dove_pcie_setup()
65 	pp->res.name = pp->mem_space_name;  in dove_pcie_setup()
66 	if (pp->index == 0) {  in dove_pcie_setup()
67 		pp->res.start = DOVE_PCIE0_MEM_PHYS_BASE;  in dove_pcie_setup()
68 		pp->res.end = pp->res.start + DOVE_PCIE0_MEM_SIZE - 1;  in dove_pcie_setup()
70 		pp->res.start = DOVE_PCIE1_MEM_PHYS_BASE;  in dove_pcie_setup()
71 		pp->res.end = pp->res.start + DOVE_PCIE1_MEM_SIZE - 1;  in dove_pcie_setup()
73 	pp->res.flags = IORESOURCE_MEM;  in dove_pcie_setup()
74 	if (request_resource(&iomem_resource, &pp->res))  in dove_pcie_setup()
76 	pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);  in dove_pcie_setup()
87 	if (bus == pp->root_bus_nr && dev > 1)  in pcie_valid_config()
96 	struct pci_sys_data *sys = bus->sysdata;  in pcie_rd_conf()
97 	struct pcie_port *pp = sys->private_data;  in pcie_rd_conf()
101 	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {  in pcie_rd_conf()
106 	spin_lock_irqsave(&pp->conf_lock, flags);  in pcie_rd_conf()
107 	ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);  in pcie_rd_conf()
108 	spin_unlock_irqrestore(&pp->conf_lock, flags);  in pcie_rd_conf()
116 	struct pci_sys_data *sys = bus->sysdata;  in pcie_wr_conf()
117 	struct pcie_port *pp = sys->private_data;  in pcie_wr_conf()
121 	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)  in pcie_wr_conf()
124 	spin_lock_irqsave(&pp->conf_lock, flags);  in pcie_wr_conf()
125 	ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);  in pcie_wr_conf()
126 	spin_unlock_irqrestore(&pp->conf_lock, flags);  in pcie_wr_conf()
144 	if (dev->bus->parent == NULL && dev->devfn == 0) {  in rc_pci_fixup()
147 		dev->class &= 0xff;  in rc_pci_fixup()
148 		dev->class |= PCI_CLASS_BRIDGE_HOST << 8;  in rc_pci_fixup()
150 			r->start = 0;  in rc_pci_fixup()
151 			r->end   = 0;  in rc_pci_fixup()
152 			r->flags = 0;  in rc_pci_fixup()
159 dove_pcie_scan_bus(int nr, struct pci_host_bridge *bridge)  in dove_pcie_scan_bus()  argument
163 	if (nr >= num_pcie_ports) {  in dove_pcie_scan_bus()
165 		return -EINVAL;  in dove_pcie_scan_bus()
168 	list_splice_init(&sys->resources, &bridge->windows);  in dove_pcie_scan_bus()
169 	bridge->dev.parent = NULL;  in dove_pcie_scan_bus()
170 	bridge->sysdata = sys;  in dove_pcie_scan_bus()
171 	bridge->busnr = sys->busnr;  in dove_pcie_scan_bus()
172 	bridge->ops = &pcie_ops;  in dove_pcie_scan_bus()
179 	struct pci_sys_data *sys = dev->sysdata;  in dove_pcie_map_irq()
180 	struct pcie_port *pp = sys->private_data;  in dove_pcie_map_irq()
182 	return pp->index ? IRQ_DOVE_PCIE1 : IRQ_DOVE_PCIE0;  in dove_pcie_map_irq()
205 		pp->index = index;  in add_pcie_port()
206 		pp->root_bus_nr = -1;  in add_pcie_port()
207 		pp->base = base;  in add_pcie_port()
208 		spin_lock_init(&pp->conf_lock);  in add_pcie_port()
209 		memset(&pp->res, 0, sizeof(pp->res));  in add_pcie_port()